JPS62155591U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a video signal processing device according to an embodiment of the present invention, and FIG. 2 is a time chart for explaining its operation. 1... Decoder, 2... First DC clamp circuit (DC clamp circuit for luminance signal Y), 3... Second
DC clamp circuit (DC clamp circuit for color difference signal R-Y), 4...3rd DC clamp circuit (DC clamp circuit for color difference signal B-Y), 5...1st A/
D converter (A/D converter for luminance signal Y)
, 6...Analog switch, 7...Second A/D converter (A/D for color difference signals R-Y, B-Y)
converter), 8...RY latch circuit, 9...
...BY latch circuit, 10...sampling clock generation circuit, 11...counter, 12...phase shift circuit.

Claims (1)

[Claims for Utility Model Registration] A sampling clock generation circuit; a counter for generating an analog switch switching clock by dividing the sampling clock from the sampling clock generation circuit into 1/4; A phase shift circuit that creates two types of data latch clocks whose phases are shifted by one clock to the plus side and minus side, and a phase shift circuit that demodulates the video signal to generate a luminance signal Y and a color difference signal R.
A decoder that separates Y, B-Y, and these luminance signals Y and color difference signals R-Y, B-Y
three DC clamp circuits that individually reproduce the DC current, and A/D converts the analog luminance signal Y from the DC clamp circuit for the luminance signal Y at the input timing of the sampling clock from the sampling clock generation circuit. a first A/D converter that outputs Y digital data; and a first A/D converter that outputs Y digital data;
an analog switch that alternately inputs the analog color difference signal RY from the C clamp circuit and the analog color difference signal BY from the DC clamp circuit for the color difference signal BY and converts it into a time-divided serial analog signal; At the input timing of the sampling clock from the sampling clock generation circuit, the serial analog signals of the time-divided color difference signals R--Y and B--Y are A/D converted to R--Y digital data and B--. A second A that outputs serial digital data in which Y digital data is arranged alternately in chronological order.
RY, B output from the second A/D converter at the timing of input of one of the two data latch clocks from the /D converter and the phase shift circuit. RY latch circuit that latches only RY digital data out of Y serial digital data, and the second A/D at the timing of input of the other data latch clock from the phase shift circuit.
A video signal processing device comprising a BY latch circuit that latches only BY digital data out of RY and BY serial digital data output from a converter.