JPS62154785A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To miniaturize an MOS transistor and to enhance drain withstanding voltage, by providing a conducting layer, which is formed on a substrate through an insulating film so that the layer is contacted with the side parts of impurity doped regions that are formed in the surface region of a semiconductor layer protruded on the substrate, with a specified interval being provided. CONSTITUTION:A semiconductor layer 12 is protruded on a specified region of a substrate 11. Impurity doped regions 24 and 25, which have the reverse conductivity type with respect to the semiconductor layer 12, are formed in the surface region of the layer 12 with a specified interval being provided. A gate electrode 27 is formed at a part between the impurity doped regions 24 and 25 on the semiconductor layer 12 through an insulating film 13. A conducting layer 20 is formed on the substrate 11 through an insulating film 16 so that the layer 20 is contacted with the side parts of the impurity doped regions 24 and 25. For example, on an N-type epitaxial Si layer 12 on the P-type Si substrate 11, the P-type low impurity concentration source and drain regions 21 and 22 are formed. The N-type polycrystalline Si gate electrode 27 is provided through the gate SiO2 film 12. The P-type polycrystalline Si layer 20 and Al electrodes 28 and 29 are provided through the SiO2 film 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device having a structure in which an electrode is taken out from a side wall of a single crystal semiconductor region, and a method for manufacturing the same.

[Background of the invention]

An example of the structure of a conventional MOS transistor is shown in FIG. In the figure, 1 is an n-type Si substrate, 2 is a silicon substrate for element isolation.
3.7 is a protective 5LO2 film, 4.5 is a p-type source and drain layer, 6 is an n-type polycrystalline Si gate electrode, 8 is a gate Sin film, and 9.10 is an M electrode. In this structure, element isolation is performed using the SiO□ film 2 using a selective oxidation method, and by doping impurities using the Si electrode 6 as a mask, the impurity doped layers 4 of the source and drain are formed in a self-aligned manner. .5 is formed.

As integrated circuits become more highly integrated, the channel length of the MOS transistors that make up the circuits becomes shorter, and the length becomes 1 /
I'm trying to get below 7+11. When the channel length becomes less than 1, the electric field is concentrated between the highly doped source/drain region and the channel region.1 A drain breakdown voltage of 5V or more, which is required for normal MOS memory or logic, is obtained. things become difficult. For this reason,
There was a problem in that it was difficult to miniaturize the elements.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device and its manufacturing method that can eliminate the problems of the prior art described above, achieve miniaturization and high breakdown voltage of semiconductor devices, and in particular miniaturize MOS transistors and increase drain breakdown voltage. It is about providing.

Another object of the present invention is to provide a 5ICOS <Sidewall base contact structure (Sidewall base contact structure) with a structure in which electrodes are taken out from the sides of the base region.
An object of the present invention is to provide a MOS transistor that can be formed on the same substrate as a bipolar transistor having a ContactStructure) structure.

[Summary of the Invention] In order to achieve the above object, the semiconductor device of the present invention has a semiconductor layer formed at a predetermined interval in a surface region of a semiconductor layer protruding on a predetermined region of a substrate. an impurity-doped region having a conductivity type of
-m pole, and at least a conductive layer that is in contact with a side of the impurity-doped region and formed on the substrate with an insulating film interposed therebetween.

The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a protruding semiconductor layer on a predetermined region of a semiconductor layer; and forming a conductive layer on the substrate so as to be in contact with a side of the semiconductor layer via an insulating film. a step of forming a gate electrode on the semiconductor layer via an insulating film; and a step of introducing an impurity into the surface region of the semiconductor layer using the gate electrode as a mask to form the half-body layer. forming impurity-doped regions having opposite conductivity types.

When the present invention is applied to a MOS transistor, the source and drain electrodes are taken out from the side of the semiconductor layer in which the source and drain regions are formed. Also.

By combining a MOS transistor with such a structure on the same substrate as a bipolar transistor with a 5ICO5 structure in which electrodes are taken out from the sides of the base region,
A high-performance Bi-CMO8 structure can also be realized.

[Embodiments of the invention]

FIG. 1 shows a first embodiment of the semiconductor device of the present invention.
A cross-sectional structure of an OS transistor is shown.

In the figure, 11 is a p-type Si substrate, 12 is an n-type epitaxial Si layer, and 16, 18, 19, and 26 are Sio films.

13 is a gate Sj, O□ film, 20 is a p-polycrystalline Si layer,
21.22 is the P-type cavity impurity concentration source, train region,
24.25 are p-type low impurity concentration source and drain regions,
27 is an n-crystal polycrystalline SL gate electrode, and 28 and 29 are the closest electrodes.

In the structure of this embodiment, as shown in the figure, the source and drain regions extend in the horizontal and vertical directions, so the area can be reduced compared to a conventional MOS transistor that extends only in the horizontal direction. Elements can be formed finely. In addition to this structure, since the insulating film 1G is provided under the polycrystalline silicon film 20 for drawing out the FTT pole, the parasitic capacitance between the substrate and the impurity doped region can be reduced. Further, low concentration source and drain regions 24 and 25 and high concentration source and drain regions 21
．． 22, it is possible to achieve a higher breakdown voltage than the MOS transistor shown in FIG. In this example, the breakdown voltage is improved by about 20% compared to the conventional MOS transistor shown in FIG.

Next, a method for manufacturing the MOS transistor shown in FIG. 1 will be explained using FIGS. 3(A) to 3(G).

First, as shown in FIG. 3A, an n-type epitaxial Si layer 12 is grown on a p-type S] substrate 11. As shown in FIG.

Next, a SiO2 layer 13 is formed using a thermal oxidation method, and a C
Si, N, layer 14 and Sio2 layer 15 using VD method
form.

Thereafter, the three layers 40 consisting of the Si layer 13.15 and the Si N4 layer 14 are patterned using a conventional photoetching technique (FIG. 3(B)).

Next, the Si pittaxial layer 12 is etched using a dry etching technique to form convex regions of Si. Thereafter, a N4 film 14' is provided on the side wall of the convex Si region using the CVD method (FIG. 3(C)).

Next, as shown in FIG. 3(D), this SL, N4 film 1
4' as an oxidation-resistant mask, thermal oxidation is performed, and S i02
Form layer 16. After removing the Si, N, and film 14', a polycrystalline SL layer 17 is buried using a known planarization technique.

Next, after forming a layer 819 on the Si◯2 film 18, the polycrystalline Si layer 17 is doped with B (boron) by ion implantation and heat treated.

Inside the convex Si region, p-wall high concentration source and drain regions 21 and 22 are formed, and then the third layer 40 is removed (third
Figure (E)).

Next, after depositing a polycrystalline Si layer and doping the polycrystalline Si layer with phosphorus, a normal photolithography technique is used to form a gate electrode 27 of the MOS as shown in FIG. 3(F). form.

After this, as shown in FIG. 3 CG), the polycrystalline n-type S
The i-gate electrode 27 is covered with a Sio film 26, and using the gate electrode 27 as a mask, B is doped using ion implantation to form p-type low concentration source and drain regions 24 and 25.
form. At this time, in order to achieve high breakdown voltage, a p-type source,
The impurity concentration of the drain layers 24 and 25 is set lower than that of the P-type source and drain layers 21 and 22.

After this, as shown in FIG.
A two-pole electrode 29 is formed to complete a P-channel MO8+- transistor as shown in FIG. It goes without saying that an N-channel MOS transistor can be formed by reversing all the conductivity types in the above process.

FIG. 4 shows a cross section of a MOS transistor according to a second embodiment of the present invention. In this embodiment, third impurity doped layers 3 and 32 are further formed in the structure shown in FIG.

The impurity concentration of the third impurity-doped layer 31.32 is intermediate between the impurity concentration of the first impurity-doped layer 21.22 and the impurity concentration of the second impurity-doped layer 24.25. That is, an SiO2 film 30 is further provided as a spacer on the sidewall of the SiO2 film 26 formed on the sidewall of the gate electrode 27 of the MoS transistor.
ly Doped Drain) structure or GLDD
(Graded LDD) structure is realized.

With this structure, high breakdown voltage and reduction in series resistance can be achieved.

FIG. 5 shows a cross section of an example of an N-channel MOS transistor according to a third embodiment of the present invention. In the figure, 33 is n
type buried layer, 34 is a p-type convex region, 35 is n-type polycrystalline Si
Layer 36.37 is an n-type high concentration source.

38 and 39 indicate n-type low concentration source and drain regions. In this structure, the area of the element is small, so
In addition to being excellent in α-ray resistance (same in the first and second embodiments), the p-type Si substrate 11 and the p-type convex region 3
Since the n-type buried layer 33 provided between 4 and 4 acts as a barrier against alpha rays, this structure has the advantage that the strength against alpha rays can be further increased compared to the structures of the first and second embodiments. have

FIG. 6 shows a cross section of a semiconductor device according to a fourth embodiment of the present invention. This embodiment shows an example in which a MOS transistor according to the present invention and a bipolar transistor with a 5ICO8 structure in which an electrode is taken out from the side wall of a base region are formed on the same substrate, in which 44 is an n-channel MOS transistor, and 45 is an p-channel MQS transistor, 46 is 5
NPN bipolar transistor with Xcos structure, 40 is an n-type polycrystalline Si layer, 41 is an n-type impurity doped region, 42
．． 43 is a p-type impurity doped region. As described above, since the MOS transistor according to the present invention has a structure in which the source and drain electrodes are taken out from the side, it can be formed on the same substrate as a 5ICOS bipolar transistor, which has a structure in which the base electrode is taken out from the side. i
- A CM OS device can be realized. In this example, the circuit speed of the element could be improved by about 30% compared to the conventional B1-CMOS device.

FIG. 7 shows a cross section of a semiconductor device according to a fifth embodiment of the present invention. This embodiment is almost the same as the fourth embodiment shown in FIG.
An n-type buried layer 47 is provided in the P-type Si substrate 11 under the type impurity doped layer 34. In this example as well, a high-performance B1-CMOS device could be realized as in the fourth example.

〔Effect of the invention〕

As described above, according to one aspect of the present invention, it is possible to achieve miniaturization of elements and increase in breakdown voltage in a MOS transistor. In addition, MOS transistors can be
Since it can be formed on the same substrate as the ICOS bipolar transistor, a high-performance Bi-CM OS device can be realized.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a MOS transistor according to a first embodiment of the semiconductor device of the present invention, FIG. 2 is a cross-sectional view of an example of a conventional MoS transistor, and FIGS. FIG. 4 is a process cross-sectional view showing an example of a method for manufacturing a semiconductor device;
5, 6, and 7 are the second and third embodiments of the present invention, respectively.
FIG. 3 is a cross-sectional view of a semiconductor device according to a fourth and a fifth embodiment. 1... N-type Si substrate 11... P-type Si substrate 2
, 3, 7.8.1:3. 15.16.18.19.2
6.3°...S io2 film 4, 5.21.22.24.25.31.32.34.
42.43...p-type impurity doped layer 6.27.35.40-n polycrystalline Si layer 9.10.2
8.29... All electrode 12... N-type epitaxial layer 14, 14'... Si3N4 film 17... Polycrystalline Si layer 20... P-type polycrystalline 51M 36, 37.38.39. 41-n type impurity doped layer 3
3.47...n-type buried layer

Claims (2)

[Claims] (1) An impurity-doped region having a conductivity type opposite to that of the semiconductor layer formed at a predetermined interval in a surface region of a semiconductor layer protruding above a predetermined region of a substrate, and a region between the impurity-doped region. A semiconductor comprising at least a gate electrode formed on the semiconductor layer with an insulating film interposed therebetween, and a conductive layer in contact with a side of the impurity doped region and formed on the substrate with an insulating film interposed therebetween. Device. (2) forming a protruding semiconductor layer on a predetermined region of the substrate; forming a conductive layer on the substrate so as to be in contact with a side of the semiconductor layer via an insulating film; forming a gate electrode through an insulating film, and using the gate electrode as a mask, introducing an impurity into the surface region of the semiconductor layer to form an impurity-doped region having a conductivity type opposite to that of the semiconductor layer. A method for manufacturing a semiconductor device, comprising the steps of: