JPS62154661A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of dielectric breakdown in an MIS-type capacitor element and thereby to improve a yield and reliability by a construction wherein a protective diode formed in a semiconductor substrate is connected to both electrodes of the MIS-type capacitor element in an integrated circuit device. CONSTITUTION:An N<+> region formed under a thin SiO2 film 8 functions as a semiconductor electrode layer of an MIS-type capacitor, and an N<+> diffusion layer 15, the thin SiO2 film 18 and a metal electrode layer 19 constitute an MIS-type capacitor element. The metal electrode layer 19 is connected to a P-type region 16 constituting a diode between the layer 19 and an N-type epitaxial layer 12, and the N-type epitaxial layer constitutes a diode with a P-type silicon substrate 11. Accordingly, the semiconductor device forms an equivalent circuit as shown by the figure, and when a high voltage is impressed on the metal electrode layer 19 of the MIS-type capacitor, a current flows to the substrate 11 through two serial and reverse diodes connected to the metal electrode layer 19 through the intermediary of a wiring 20. By this construction, an excessive increase in charge on the metal electrode layer 19 is avoided and dielectric breakdown is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to an improvement in a semiconductor integrated circuit device having an MIS type capacitor element. 1 [Technical Background of the Invention] FIG. 8 shows a conventional M provided in a semiconductor integrated circuit device.
IS type (Mctal-1nsulator-Sem1c
(onductor) shows the cross-sectional structure of a capacitor.

Here, the MIS type capacitor is a capacitive element configured by interposing a thin insulating film made of 5i02, Si3N4, etc. between a metal electrode layer and a semiconductor electrode layer.

In the figure, 1 is a P-type silicon substrate.

Various elements such as bipolar transistors constituting an integrated circuit are formed in a region (not shown) of the silicon substrate. Further, a thick field oxide film 2 is formed on the surface of the silicon substrate 1 to cover a portion other than the element region, and a metal electrode layer 4 is formed in the capacitor region with a thin insulating film 3 interposed therebetween. A metal electrode 5 is formed near the metal electrode layer 4 and is in ohmic contact with the silicon substrate 1 through a contact hole formed in the field oxide film 2. In this case, the P-type silicon substrate 1 and the metal electrode layer 4 function as electrode plates of a capacitor, and the thin insulating film 3 interposed between them functions as a dielectric.

FIG. 9 is a sectional view showing another example of a conventional MIS type capacitor element. In this example, a polycrystalline silicon layer 6 formed on field oxide film 2 is used as a semiconductor electrode layer constituting a capacitor. A metal electrode layer 4 of the capacitor is formed via a thin insulating film 3' formed to cover the surface of this polycrystalline silicon layer 6.

Note that a contact hole is opened in the thin insulating film 3', and a metal electrode 5' is formed in ohmic contact with the polycrystalline silicon electrode layer 6.

Capacity 1aC in the capacitors shown in Figures 8 and 9 above
is the area A of the part where the electrodes on both sides are laminated with the thin insulating films 3 and 3' interposed, and the thickness t1 of the thin insulating film 3.3'
It is determined by the dielectric constant of the insulating films 3 and 3'. Therefore, as one means of forming a large capacitance capacitor, a method is used in which the thickness t of the insulating films 3, 3' is reduced.

[Problems with background technology]

As mentioned above, in the conventional MIS type capacitor, the insulating film 3
．． By reducing the film thickness t of 3', the capacitance per unit area increases, but at the same time, the withstand voltage of the insulating film decreases. For this reason, when a high voltage is applied to the capacitor for various reasons, such as in the following case, dielectric breakdown occurs and the capacitor becomes inoperable.

First, in recent manufacturing processes using dry etching, a voltage exceeding the withstand voltage of the capacitor is often applied to the capacitor during the manufacturing process. Dielectric breakdown of the capacitor in this case significantly reduces manufacturing yield.

In particular, when a capacitor becomes isolated at the stage where the first layer metal wiring process is completed in a multilayer wiring process, the metal electrode layer of the capacitor is likely to be charged up, so that the occurrence of defects becomes more noticeable.

The second case is when the capacitor is charged up due to a surge applied from the outside through the pin during the IC assembly process and during the use of the IC, causing dielectric breakdown.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent dielectric breakdown from occurring in an MIS type capacitor element formed in a semiconductor integrated circuit device during the manufacturing process and use of the device.

[Summary of the invention]

In the present invention, a protective diode formed in a semiconductor substrate is connected to both electrodes of a MIS type capacitor element in an integrated circuit device.

Thereby, when the electrode of the capacitor is excessively charged up, the charge can be released to the semiconductor substrate side through the protective diode, thereby preventing dielectric breakdown of the capacitor.

[Embodiments of the invention]

FIG. 1 is a sectional view showing one embodiment of the present invention. In the figure, 11 is a P-type silicon substrate. On the silicon substrate 11, an epitaxially grown N-type silicon layer 12 is formed. A P-type isolation diffusion layer 13 is formed from the surface of the N-type epitaxial layer 12 to reach the P-type silicon substrate 11, thereby electrically separating each element region. In the element region for the capacitor, an N-type epitaxial layer 12 and a P
An N0 type buried region 14 is formed between the silicon plate 11 and the silicon plate 11 . Then, an N+ type scattering layer 15 reaching the buried region 14 is formed. On the other hand, the cable for the diode]
A P ten-type 8r1 region 16 is provided in the '- region, and a P ten-type 8r1 region 16 is provided between it and the NF epitaxial layer 12, which functions as a diode.
An N junction is formed. J-3e The surface of the epitaxial layer 12 on which various impurity regions are formed is covered with a thick field oxide film 17, but only the element region for the capacitor is covered with a thin 5i02 film 18. (The metal electrode layer 19 of the capacitor is formed covering the thin 5i02 film 18.
is connected to the P main region 16 constituting the diode element via a metal wiring 20. 21 is the N-type diffusion layer 1
This is a metal electrode provided in ohmic contact with 5. Note that other elements such as bipolar transistors are formed in regions not shown.

In the above embodiment, N is formed under the thin 5i02 film 18.
The 10 region functions as the semiconductor electrode layer of the MIS type capacitor, and therefore the N10 diffusion layer 15, the thin 5i02 film 18 and the metal electrode layer 19 constitute the MIS type capacitor element. The metal electrode layer 19 is connected to the P essential region 16 which forms a diode with the N-type epitaxial layer 12, and the N-type epitaxial layer forms a diode with the P-type silicon substrate 11. . Also, MIS
The semiconductor electrode layer of the type capacitor, that is, the N0 type diffusion layer 15 forms a diode with the P type silicon substrate 11. Therefore, the semiconductor device having the structure shown in FIG. 1 is represented in terms of an equivalent circuit as shown in FIG. 2. As a result, when a high voltage is applied to the metal electrode layer 19 of the MIS type capacitor, a current flows to the substrate 11 through the two series and oppositely directed diodes connected to the metal electrode layer 19 via the wiring 20. 1, excessive charge-up of the metal electrode layer 19 is avoided and dielectric breakdown is prevented. Furthermore, since the two diodes connected to the metal electrode layer 19 are connected in series and in opposite directions, the same protective effect can be obtained whether the voltage applied to the metal electrode layer 19 is 0 or -. That is, in either case, one of the two diodes that is reverse biased will break down and a current will flow.

Due to the above-mentioned effects, the embodiment shown in FIG. 1 can significantly reduce the incidence of dielectric breakdown defects in capacitors during the manufacturing process. For example, in the case of an IVI I S type capacitor with a thin 5i02 film 18 of 50 OA (normal breakdown voltage is 15 to 50 V), the yield in a conventional example without a protection diode is 25 to 36%. For,
The yield in the above example was 100%, a remarkable improvement. Further, since the protection diode 1- acts on the same function even during operation of the device, dielectric breakdown failure due to surge input during use is significantly reduced, and reliability is greatly improved.

Next, further preferred embodiments of the present invention will be described.

FIG. 3 is a sectional view showing another embodiment of the present invention. In this embodiment, a P-shaped diffusion layer 22 is formed as the semiconductor electrode layer of the MIS type capacitor instead of an N-type diffusion layer. The rest of the structure is exactly the same as the embodiment shown in FIG. In this embodiment, the semiconductor electrode layer of the MIS type capacitor, that is, the P-shaped diffusion layer 22 is formed by the N-type epitaxial layer 12.
A diode is formed between the N-type epitaxial layer 12 and the P-type silicon substrate 11. Therefore, the equivalent circuit diagram of this embodiment is shown in FIG. 4, and the semiconductor electrode layer 2 of the MIS type capacitor
2 is also connected in series with two diodes in opposite directions.

FIG. 5 is a sectional view showing still another embodiment of the present invention.
As in the conventional example shown in the figure, a polycrystalline silicon layer formed on a field oxide film 17 is used as a semiconductor electrode layer of an MIS type capacitor.

That is, 1, in this embodiment, a thin 5i02 film 18' is formed covering the surface of the polycrystalline silicon layer 23;
A metal electrode layer 19 of an MIS type capacitor is formed on the two films. Further, in this embodiment, the epitaxial layer 1
Two P-type head regions 161 and 162, which constitute a protection diode, are independently provided between the two. A metal electrode layer 19 is connected to one of the P-type regions 16+ via a wiring layer 20, and a metal electrode 21 is provided in the other P-type head region 162 in ohmic contact with the polycrystalline silicon layer 23. is connected. The equivalent circuit of this embodiment is as shown in FIG. 6, in which two diodes in series and opposite directions are connected to each of the electrode layers of the MIS type capacitor.

The embodiments shown in FIGS. 3 and 5 above have a greater effect than the embodiment shown in FIG. 1 in preventing dielectric breakdown due to charge-up, and also have the following special effects. . In other words, since two diodes are connected in series and in opposite directions to both electrodes of the MIS type capacitor, the two electrodes of the capacitor are not directly connected, as shown in the circuit diagram in Figure 7, for example. In addition, when used in a place where the potential relationship between the two electrodes is reversed, dielectric breakdown of the MIS type capacitor can be prevented in the same way as described above, regardless of which side the + or - surge input is applied.

In the above embodiments, 5i02 was used as the thin insulating film of the MIS type capacitor, but the present invention can be similarly applied to cases where other insulating films such as Si3N4 film are used.

In addition, in the above embodiment, the protective diode element is
The protection diode may be provided adjacent to the MIS type capacitor or separated from the capacitor element as long as it is connected to the electrode layer of the MIS type capacitor.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to prevent dielectric breakdown from occurring in MIS type capacitor elements formed in a semiconductor integrated circuit device in the manufacturing process of the device, thereby significantly improving the manufacturing yield. can be used, and MI during use
This provides remarkable effects such as preventing destruction of the S-type capacitor and improving reliability.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the main structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIG. 3 is a cross-sectional view showing another embodiment of the present invention. 4 is an equivalent circuit diagram thereof, FIG. 5 is a sectional view showing still another embodiment of the present invention, FIG. 6 is an equivalent circuit diagram thereof, and FIG.
8 and 9 are cross-sectional views showing the structure of a conventional MIS type capacitor, respectively. DESCRIPTION OF SYMBOLS 11... P type silicon substrate, 12... N type epitaxial silicon layer, 13... P ten type isolation diffusion layer, 14... N small buried region, 15... N+ diffusion layer, 16 ．． 16t, 162...P ten area,
17...Field oxide film, 18.18'...Thin 5i02 film, 19...Metal electrode layer, 20...Wiring layer, 21...Metal electrode, 22...P+ type diffusion layer, 23
...Polycrystalline silicon layer. Figure 5 Figure 1 Lower Figure 7 Figure 8 Figure 9

Claims (7)

[Claims] (1) A protective diode formed in a semiconductor substrate is connected to both electrodes of a MIS type capacitor element in an integrated circuit device, and a protection diode is connected to at least one of the electrodes in the opposite direction and in series. A semiconductor device characterized by connecting two diodes. (2) The semiconductor device according to claim (1), wherein one diode is connected to one electrode of the MIS type capacitor. (3) The semiconductor device according to claim (1), characterized in that two diodes coupled in series in opposite directions are connected to both electrodes of the MIS type capacitor. (4) a diode element comprising an island-shaped second conductivity type region formed in a first conductivity type semiconductor substrate and a first conductivity type impurity region formed within the second conductivity type region; A thick insulating film formed covering the surface of a semiconductor substrate,
An MIS type capacitor element in which a metal electrode layer is laminated on a semiconductor electrode layer via a thin insulating film, and a wiring connecting the metal electrode layer of the MIS type capacitor element to a first conductivity type impurity region constituting the diode element. , and a diode connected to the semiconductor electrode layer of the MIS type capacitor element,
The semiconductor device according to item (2) or item (3). (5) The semiconductor electrode layer constituting the MIS type capacitor is a second conductivity type semiconductor conductive region formed on the first conductivity type semiconductor substrate, and the diode connected to the semiconductor electrode layer is a second conductivity type semiconductor conductive region. 4. The semiconductor device according to claim 4, wherein the semiconductor device is a parasitic diode formed between a semiconductor region and the first conductivity type semiconductor substrate. (6) The semiconductor electrode layer constituting the MIS type capacitor is a first conductivity type semiconductor region formed in the second conductivity type semiconductor region in the first conductivity type semiconductor substrate, and is connected to the semiconductor electrode layer. The diode is a parasitic diode formed between the first conductivity type semiconductor region and the second conductivity type semiconductor region and between the second conductivity type semiconductor region and the first conductivity type semiconductor substrate. A semiconductor device according to claim (4). (7) The semiconductor electrode layer constituting the MIS type capacitor is a semiconductor layer formed on the thick insulating film, and the diode connected to the semiconductor electrode layer is formed on the first conductivity type semiconductor substrate. Claim 4 is another diode element comprising an island-shaped second conductivity type region and a first conductivity type impurity region formed within the second conductivity type region. ) The semiconductor device described in item 2.