JPS62154644A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate pinholes in an interlayer insulating film and voids in aluminum wirings by lowering a second aluminum sintering than a first aluminum sintering at temperature. CONSTITUTION:After a predetermined Locos oxide film, a gate oxide film, a polysilicon gate, and a source.drain diffused layer are formed and processed on a silicon substrate 1, an interlayer insulating film made of PSG 2 for covering them is formed, and first layer aluminum wirings 3 are then formed. Then, a first aluminum sintering is executed at 450 deg.C for 30min in N2/H2 mixture gas atmosphere. A silicon nitride film 4 is then deposited by a plasma CVD method to form an interlayer insulating film. Subsequently, after a through hole is opened in the plasma silicon nitride film, second layer aluminum wirings 5 are formed, a second aluminum sintering is performed, for example, at 380 deg.C for 30min in N2/H2 mixture gas atmosphere to complete aluminum 2-layer wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of heat treating multilayer wiring of a semiconductor device.

BACKGROUND OF THE INVENTION In recent years, in order to increase the integration and speed of LSI elements, the number of LSI devices having a multilayer wiring structure has been increasing, and alloys containing Afi as a main component are generally used as wiring materials.

As an example of a conventional heat treatment method for multilayer wiring, the manufacturing process of a MOS type semiconductor device will be described with reference to FIGS. 2(a) to 2(C). Note that FIG. 2 shows the manufacturing process of the A52 layer wiring, and for the sake of simplicity, the transistor region is not shown.

As shown in FIG. 2 (&), first, PSG is applied so as to cover the circuit elements (not shown in the figure) on the silicon substrate 1.
After forming the interlayer insulating film consisting of film 2, the first layer of film 4 is formed.
Wiring 3 is formed. After this, as shown in FIG. 2(b), for example, the first
Apply Ad sintering. Next, a silicon nitride film 4 is deposited by plasma CVN method to form an interlayer insulating film.

Subsequently, as shown in FIG. 2(C), a through hole (not shown in the figure) is formed on this plasma silicon nitride film, and then a second layer of Ad wiring 5 is formed. For example, under a horse/H2 mixed gas atmosphere, at a temperature of 450°C, the second
By performing Al sintering, the A//2 layer wiring is completed. However, at this time, pinholes 6 are formed in the plasma silicon nitride film 4, which is an interlayer insulating film, and electrical leakage is likely to occur between the first layer Ad wiring 3 and the second layer Ad wiring 6. At the same time, voids occur in the first layer of Ad wiring 3. The main reason why pinholes 6 and voids occur is that moisture and Ar gas introduced into the A5 film when sputtering Al for the first-layer mu-e wiring 3 expand during the second Ad sintering process. This is thought to be for the purpose of

This is because although the first Ad resin is applied, the temperature is as low as 380° C., so moisture and Ar gas cannot be sufficiently removed from the A5 wiring.

Problems to be Solved by the Invention Pinholes in the interlayer insulating film cause electrical leakage, resulting in problems in device characteristics. Furthermore, it is clear that when a void occurs in the human e-wiring, reliability problems such as electromigration are likely to occur because the cross-sectional area of the Al wiring in that portion becomes smaller.

Means for Solving the Problems In order to solve the above problems, the present invention provides at least one interlayer insulating film and at least two conductive layers on a semiconductor substrate directly or via an insulating film. comprising the steps of alternately and sequentially laminating the conductive layers so as to have the conductive layers on a portion of both surfaces of the interlayer insulating film, and sequentially sintering the conductive layers after lamination, and where n is an integer, n There is provided a method for manufacturing a semiconductor device, characterized in that the sintering temperature of the conductive layer stacked as the th conductive layer is higher than the sintering temperature of the conductive layer stacked as the (n+1)th conductive layer.

According to the present invention, since the second Ad resin has a lower temperature than the first Ad resin, the first Ad resin has a higher temperature.
Moisture, Ar gas, etc. that were not released during sintering are not released during the second Ad sintering at a lower temperature.

That is, problems in terms of characteristics and reliability are solved without generating pinholes in the interlayer insulating film or voids in the bottom line of the first layer.

EXAMPLE Hereinafter, an example in which the present invention is applied to the manufacture of an MO5 type semiconductor device will be described using cross-sectional views showing the manufacturing steps of FIGS. 1(a) to 1(C). For simplicity, A52 is shown in the figure.
Only layer wiring portions are shown, and transistor regions are not shown.

As shown in FIG. 1 (IL), first, a predetermined Lacos oxide film, a gate oxide film, a polysilicon gate, a source/drain diffusion layer, etc. are formed on a silicon substrate 1, and then a PSG 2 that covers these is formed. An interlayer insulating film consisting of is formed, and then a first layer of mu wiring lines 3 is formed. After this, the first test was carried out for 30 minutes at 450°C in a N2/H2 mixed gas atmosphere.
Apply Ad resin.

Next, as shown in FIG. 1(b), a silicon nitride film 4 is deposited by the plasma CVD method to form an interlayer insulating film.

Subsequently, as shown in FIG. 1(C), a through hole (not shown) is formed on this plasma silicon nitride film, and then a second layer of A5 wiring 6 is formed. For example, the 12-layer wiring is completed by performing a second sintering process at 380° C. for 30 minutes in an N2/H2 mixed gas atmosphere.

In the above embodiment, since the temperature of the second Ad resin is lower than the temperature of the first Al sinter, gas is not released from the first layer of human e-wire during heat treatment of the second e-sinter. There are no pinholes in the interlayer insulating film and A in the first layer.
e No voids were generated during the wiring.

In addition, in the example, the first Aβ temperature was 450'C.
1 The second Ae sinter temperature was 380 °C, but in other experiments, similar effects were found when the first Ad sinter temperature was 20~j OO'C higher than the second Ad sinter temperature. It was confirmed. In addition, in this embodiment, AJg
Although we have explained two-layer wiring, the same effect can be obtained in A5 multilayer wiring with three or more layers as long as the sintering temperature of the nth (n integer) layer Ad wiring is higher than the sintering temperature of the (n+1)th layer Ad wiring. It is clear that this can be expected.

As described in detail, according to the present invention, pinholes do not occur in the interlayer insulating film, and voids do not occur in the A6 wiring, so that semiconductor devices that have had problems in terms of characteristics and reliability can be solved. can be obtained.

[Brief explanation of drawings]

FIGS. 1(&) to (C) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(2L) to (C) are cross-sectional views showing the manufacturing process of a conventional example. 1... Silicon substrate, 2... PSG film, 3... First layer kl wiring, 4...
Plasma silicon nitride film, 6... second layer A5 wiring, 6... pinhole 7... void. Name of agent: Patent attorney Toshio Nakao and 1 other person7-
---Void

Claims (2)

[Claims] (1) At least one interlayer insulating film and at least two conductive layers are formed on the semiconductor substrate directly or via an insulating film, and the conductive layer is formed on a portion of both surfaces of the interlayer insulating film. and a step of sequentially sintering each of the conductive layers after lamination, and where n is an integer, the sintering temperature of the n-th conductive layer is the same as that of the (n+1)th conductive layer. A method for manufacturing a semiconductor device, characterized in that the temperature is higher than the sintering temperature of the conductive layer. (2) Claims in which the conductive layer is made of an Al alloy, and the sintering temperature difference between the nth conductive layer and the (n+1)th conductive layer is within the range of 20°C to 100°C. 2. A method for manufacturing a semiconductor device according to item 1.