JPS62149140A - Manufacture of resin sealed semiconductor device - Google Patents
Manufacture of resin sealed semiconductor deviceInfo
- Publication number
- JPS62149140A JPS62149140A JP29019985A JP29019985A JPS62149140A JP S62149140 A JPS62149140 A JP S62149140A JP 29019985 A JP29019985 A JP 29019985A JP 29019985 A JP29019985 A JP 29019985A JP S62149140 A JPS62149140 A JP S62149140A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- sealed semiconductor
- burr
- notch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing And Handling Of Plastics And Other Materials For Molding In General (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半v4淳装賑の製造方法に係り、特にプラス
チックパッケージのバリ取りに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semi-V4 package, and particularly to deburring a plastic package.
第6囚は樹脂封止型半導体装置回路装置の斜視図で、斜
線部は従来の樹脂封止型半導体集積回路装置の部分断面
図である。(1)は、樹脂封止に除して、パッケージ本
体から導出される外部リード(3)と、これらを接続す
るタイバ(4)とが成す空間に発生するバリである。The sixth figure is a perspective view of a resin-sealed semiconductor device circuit device, and the shaded area is a partial sectional view of a conventional resin-sealed semiconductor integrated circuit device. (1) refers to burrs generated in the space formed by the external leads (3) led out from the package body and the tie bars (4) connecting them, in addition to the resin sealing.
と把の様な従来の樹脂封止型半導体集積回路装置は、勧
脂封止成形時に発生するバリを除去する際に、前記パッ
ケージ本体寄りのバリの一部が残る等の問題点かあ・つ
た。Conventional resin-sealed semiconductor integrated circuit devices, such as those that handle plastic molding, have problems such as some of the burrs remaining near the package body when removing burrs that occur during resin-sealing molding. Ivy.
この発明は、J:把の様な従来の樹脂封止型半導体集積
回路装置の問題点を解消するためになされたもので、バ
リのない樹脂封止型半導体装置を帰る事を目的とする。This invention was made to solve the problems of conventional resin-sealed semiconductor integrated circuit devices such as the J: grip, and aims to produce a resin-sealed semiconductor device without burrs.
この発明は、バリに切欠部を形成し、この切欠部に沿っ
てバリを除去するようにしたものである。In this invention, a notch is formed in the burr, and the burr is removed along the notch.
この発明においては、バリは切欠部に沿って本体から容
易に除去さ口る。In this invention, the burr is easily removed from the body along the notch.
第1図は、この発明の一実施例を示す断面図であり、第
6因と同一符号は同一のものを示す。FIG. 1 is a sectional view showing an embodiment of the present invention, and the same reference numerals as the sixth factor indicate the same elements.
第1図に示す様にパッケージ本体(2)とバリ+1)の
境界面に接すると共に、潟の両端部が外部リード(3)
の側面より外部リード(3)の内部に達しqいように、
溝(6a)を形成する。次VC、タイバ(4)を除去と
同時に前記バリ(1)を溝(5a)に沿って除去する。As shown in Figure 1, both ends of the lag are in contact with the interface between the package body (2) and the burr +1), and the outer leads (3)
so that it reaches the inside of the external lead (3) from the side of the
A groove (6a) is formed. Next, the burr (1) is removed along the groove (5a) at the same time as the VC and tie bar (4) are removed.
丘紀実施’Ibでは、タイバ(4)とバリ(1)を同時
に除去したが前記バリ(1)を除去してから前記タイバ
(4)を除去してもよい。In Okuki Jitsu'Ib, the tie bar (4) and burr (1) were removed at the same time, but the tie bar (4) may be removed after the burr (1) is removed.
鯖2図1=、この発明の他の実&例を示すもので溝(5
b)の断面形状をU字形にしたものである。Saba 2 Figure 1 = shows another example of this invention with a groove (5
The cross-sectional shape of b) is U-shaped.
第8図は、この発明の他の実施例を示すもので、溝(5
c)の断面形状を凹形にしたものである。FIG. 8 shows another embodiment of the present invention, in which the groove (5
The cross-sectional shape of c) is made concave.
第4図は、この発明の他の実施沙!1を示すもので、1
iiI記バリの表面裏面の両面に溝(5d、5e)を前
記外部リード(3)突出部をつなぐ面とに接する位置に
設けたものである。Figure 4 shows another embodiment of this invention! Indicates 1, 1
Grooves (5d, 5e) are provided on both the front and back surfaces of the burr described in iii.
第5図は、この発明の他の実施例を示すもので、複数の
溝(5f 、 5g )を前記外部リード(3)突出部
をつなぐ面tに接する位置と、タイバ(4)に接する位
置に設けたものである。FIG. 5 shows another embodiment of the present invention, in which a plurality of grooves (5f, 5g) are arranged at a position in contact with a surface t connecting the protruding parts of the external lead (3) and a position in contact with a tie bar (4). It was established in
J:紀実施例において溝の位置について説明したが、別
の位置でもよ(、バリの中央部に溝を設けてもよい。Although the position of the groove has been explained in the embodiment, it may be placed in another position (or the groove may be provided in the center of the burr).
この発明は以と説明したとおり、バリに切欠部を形成し
、この切欠部に沿ってバリを除去する様にしたので、バ
リの除去が容易にできる効果がある。As described above, in this invention, a notch is formed in the burr, and the burr is removed along the notch, so that the burr can be easily removed.
第1因は、この発明の一実施例を示す断面図、第2図、
第8図、第4図、第5図はこの発明の他の実施例をそれ
ぞn示す断面図、第6図は従来の樹脂封止型半導体集積
回路装置の製造方法で作らnた樹脂封止型半導体集積回
路装置の斜視図であ図において(1)はバリ、(2)は
パッケージ本体、(3)1j外部リード、(4)はタイ
バ、(5a)〜(5g)は溝である。
図中、同一符号は同一または相当部分を示す。The first factor is FIG. 2, which is a sectional view showing an embodiment of the present invention.
8, 4, and 5 are cross-sectional views showing other embodiments of the present invention, and FIG. 6 is a resin-sealed semiconductor integrated circuit device manufactured by a conventional method for manufacturing a resin-sealed semiconductor integrated circuit device. This is a perspective view of a fixed type semiconductor integrated circuit device. In the figure, (1) is a burr, (2) is a package body, (3) 1j external lead, (4) is a tie bar, and (5a) to (5g) are grooves. . In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (9)
の外部リード間に発生するバリに切欠部を形成し、この
切欠部に沿つて前記本体からバリを除去することを特徴
とする樹脂封止型半導体装置の製造方法。(1) A resin characterized in that a notch is formed in a burr generated between a plurality of external leads led out from a main body of a resin-sealed semiconductor device, and the burr is removed from the main body along this notch. A method for manufacturing a sealed semiconductor device.
位置に設けられることを特徴とする特許請求の範囲第1
項記載の樹脂封止型半導体装置の製造方法。(2) Claim 1, characterized in that the notch is provided at a position adjacent to the external lead-out lead protrusion of the main body.
A method for manufacturing a resin-sealed semiconductor device as described in 1.
ことを特徴とする特許請求の範囲第1項記載の樹脂封止
型半導体装置の製造方法。(3) The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the cutout portion is provided on both the front and back surfaces of the burr.
距離はなれて設けられることを特徴とする特許請求の範
囲第1項記載の樹脂封止型半導体装置の製造方法。(4) The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the notch is provided at a predetermined distance from the external lead projection of the main body.
する特許請求の範囲第1項記載の樹脂封止型半導体装置
の製造方法。(5) The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the cross-sectional shape of the notch is a V-shaped groove.
する特許請求の範囲第1項記載の樹脂封止型半導体装置
の製造方法。(6) The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the cross-sectional shape of the notch is a U-shaped groove.
形成されることを特徴とする特許請求の範囲第1項記載
の樹脂封止型半導体装置の製造方法。(7) The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the notch is formed by providing a protrusion on a resin-sealed mold.
る特許請求の範囲第1項記載の樹脂封止型半導体装置の
製造方法。(8) The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the notch is formed by machining.
特徴とする特許請求の範囲第1項記載の樹脂封止型半導
体装置の製造方法。(9) The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the cutout is formed by laser processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29019985A JPS62149140A (en) | 1985-12-23 | 1985-12-23 | Manufacture of resin sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29019985A JPS62149140A (en) | 1985-12-23 | 1985-12-23 | Manufacture of resin sealed semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62149140A true JPS62149140A (en) | 1987-07-03 |
Family
ID=17753033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29019985A Pending JPS62149140A (en) | 1985-12-23 | 1985-12-23 | Manufacture of resin sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62149140A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004343038A (en) * | 2003-05-12 | 2004-12-02 | Jettech Ltd | Semiconductor package having cutting groove on side flash, method of forming this cutting groove, deflashing method in semiconductor package having cutting groove |
JP2008252005A (en) * | 2007-03-30 | 2008-10-16 | Sanyo Electric Co Ltd | Deburring method, and manufacturing method of semiconductor device |
-
1985
- 1985-12-23 JP JP29019985A patent/JPS62149140A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004343038A (en) * | 2003-05-12 | 2004-12-02 | Jettech Ltd | Semiconductor package having cutting groove on side flash, method of forming this cutting groove, deflashing method in semiconductor package having cutting groove |
JP2008252005A (en) * | 2007-03-30 | 2008-10-16 | Sanyo Electric Co Ltd | Deburring method, and manufacturing method of semiconductor device |
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