JP2000058572A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000058572A
JP2000058572A JP10223072A JP22307298A JP2000058572A JP 2000058572 A JP2000058572 A JP 2000058572A JP 10223072 A JP10223072 A JP 10223072A JP 22307298 A JP22307298 A JP 22307298A JP 2000058572 A JP2000058572 A JP 2000058572A
Authority
JP
Japan
Prior art keywords
resin
semiconductor
circuit board
circuit
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10223072A
Other languages
Japanese (ja)
Inventor
Taro Yamazaki
太郎 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Miyota KK
Original Assignee
Miyota KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Miyota KK filed Critical Miyota KK
Priority to JP10223072A priority Critical patent/JP2000058572A/en
Publication of JP2000058572A publication Critical patent/JP2000058572A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To ease handling of individual semiconductor devices by forming a plurality of circuit patterns on one circuit board, mounting semiconductors and circuit component parts thereto, molding the entire body by resin, and connecting adjoining semiconductor devices by a sealing resin and/or mold resin before dividing the entire body individually. SOLUTION: A plurality of semiconductors 2 are mounted to a circuit board 1, and the entire body is subject to wire bonding, and then it is packaged by a resin 3. Circuit component parts 4 are mounted to individual semiconductors and they are molded by a mold resin 5. Further, the circuit board 1 is diced among the individual semiconductor devices, so as to form grooves 6. In this state, every semiconductor devices are connected by the thin wall parts of the packaging resin 3. When the semiconductor device is mounted to a circuit board, etc., the semiconductor devices are individually broken for use. Since the dicing is applied not for breaking the circuit board but for breaking the thin wall part of the packaging and/or mold resin, the circuit board can be broken without applying any stress.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置とその製
造方法に関するものである。The present invention relates to a semiconductor device and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】１枚の回路基板に複数の回路パターンを
形成し、半導体および回路構成部品を搭載後樹脂モール
ドし、ダイシングにより個々の半導体装置として分割す
る半導体装置の製造方法がある。2. Description of the Related Art There is a method of manufacturing a semiconductor device in which a plurality of circuit patterns are formed on one circuit board, a semiconductor and circuit components are mounted, resin-molded, and divided into individual semiconductor devices by dicing.

【０００３】図１は従来技術による半導体装置製造方法
の工程図である。（Ａ）は回路パターン（不図示）を形
成した回路基板１に半導体２を搭載しワイヤーボンディ
ング後樹脂２で封止した断面図である。（Ｂ）は更に回
路構成部品４を搭載した断面図である。（Ｃ）は前記搭
載部品をモールド樹脂５により樹脂モールドした正面図
である。（Ｄ）は回路基板１をダイシング等により切り
離した正面図である。（Ｅ）は構成部品等の搭載におい
て、隣り合う半導体装置の間隔が広くなってしまう場合
であり、隣り合う半導体装置の間の余分な回路基板１’
を切り離した正面図である。FIG. 1 is a process chart of a conventional semiconductor device manufacturing method. 1A is a cross-sectional view in which a semiconductor 2 is mounted on a circuit board 1 on which a circuit pattern (not shown) is formed, and is sealed with a resin 2 after wire bonding. (B) is a cross-sectional view in which a circuit component 4 is further mounted. (C) is a front view in which the mounting component is resin-molded with a molding resin 5. (D) is a front view in which the circuit board 1 is separated by dicing or the like. (E) is a case where the interval between adjacent semiconductor devices becomes large in mounting component parts and the like, and an extra circuit board 1 ′ between adjacent semiconductor devices.
FIG.

【０００４】図１（Ｄ）、図１（Ｅ）のいずれの場合も
回路基板１は完全に切り離している製造方法であった。[0004] In both cases of FIGS. 1D and 1E, the manufacturing method is such that the circuit board 1 is completely separated.

【０００５】[0005]

【発明が解決しようとする課題】ダイシング等により半
導体装置を完全に個々に切り離してしまうので以後の取
り扱いが一個対応になり不便であった。特に完成後の形
状が円筒状になるような半導体装置では取り扱いが面倒
であった。回路基板を完全に切り離さず切り込みを入れ
ておき、使用するときにブレークする方法もあるが、回
路基板をブレークするのは回路基板に応力が掛かり好ま
しい方法ではない。Since the semiconductor devices are completely cut off individually by dicing or the like, the subsequent handling becomes one-handed, which is inconvenient. In particular, handling is troublesome for a semiconductor device whose completed shape is cylindrical. There is also a method in which a notch is made without completely separating the circuit board, and a break occurs when the circuit board is used. However, breaking the circuit board is not a preferable method because stress is applied to the circuit board.

【０００６】図１（Ｅ）の方法では、余分な回路基板
１’を切り離すために、ダイシング時に余分な回路基板
１’が飛び散りブレードを破損することがあった。In the method shown in FIG. 1E, the extra circuit board 1 'may be cut off during the dicing to break the blade, in order to separate the extra circuit board 1'.

【０００７】[0007]

【課題を解決するための手段】１枚の回路基板に複数の
回路パターンを形成し、半導体および回路構成部品を搭
載後樹脂モールドして個々の半導体装置として分割する
半導体装置において、分割前は隣り合う半導体装置が半
導体用の封止樹脂および／またはモールド樹脂で接続す
る。SUMMARY OF THE INVENTION In a semiconductor device in which a plurality of circuit patterns are formed on a single circuit board, and a semiconductor and circuit components are mounted and then resin-molded to be divided into individual semiconductor devices, adjacent semiconductor devices are divided before dividing. The matching semiconductor devices are connected by a semiconductor sealing resin and / or a molding resin.

【０００８】１枚の回路基板に複数の回路パターンを形
成する工程と、半導体および回路構成部品を搭載する工
程と、半導体を樹脂封止する工程と、半導体および回路
構成部品を樹脂モールドする工程と、回路基板を分割し
て個々の半導体装置にする工程を有する半導体装置の製
造方法において、半導体を樹脂封止する工程で隣り合う
半導体装置が分割される部分を半導体用封止樹脂で接続
し、回路基板を分割して個々の半導体装置にする工程に
おいて、ダイシングにより回路基板を切断し、前記接続
用半導体用封止樹脂の一部は切断しないで残しておく製
造方法とする。A step of forming a plurality of circuit patterns on one circuit board, a step of mounting semiconductors and circuit components, a step of resin-sealing the semiconductor, and a step of resin-molding the semiconductor and circuit components. In a method of manufacturing a semiconductor device having a step of dividing a circuit board into individual semiconductor devices, in a step of sealing a semiconductor with a resin, a portion where an adjacent semiconductor device is divided is connected with a semiconductor sealing resin, In the step of dividing the circuit board into individual semiconductor devices, the circuit board is cut by dicing, and a part of the sealing resin for a semiconductor for connection is left uncut without cutting.

【０００９】１枚の回路基板に複数の回路パターンを形
成する工程と、半導体および回路構成部品を搭載する工
程と、半導体を樹脂封止する工程と、半導体および回路
構成部品を樹脂モールドする工程と、回路基板を分割し
て個々の半導体装置にする工程を有する半導体装置の製
造方法において、半導体および回路構成部品を樹脂モー
ルドする工程で隣り合う半導体装置が分割される部分を
モールド樹脂で接続し、回路基板を分割して個々の半導
体装置にする工程において、ダイシングにより回路基板
を切断し、前記接続用モールド樹脂の一部は切断しない
で残しておく製造方法とする。A step of forming a plurality of circuit patterns on one circuit board, a step of mounting semiconductors and circuit components, a step of resin-sealing the semiconductor, and a step of resin-molding the semiconductor and circuit components. In a method of manufacturing a semiconductor device having a step of dividing a circuit board into individual semiconductor devices, in a step of resin-molding a semiconductor and circuit components, a portion where adjacent semiconductor devices are divided is connected with a mold resin, In the step of dividing the circuit board into individual semiconductor devices, the circuit board is cut by dicing, and a part of the connection molding resin is left uncut.

【００１０】１枚の回路基板に複数の回路パターンを形
成する工程と、半導体および回路構成部品を搭載する工
程と、半導体を樹脂封止する工程と、半導体および回路
構成部品を樹脂モールドする工程と、回路基板を分割し
て個々の半導体装置にする工程を有する半導体装置の製
造方法において、半導体および回路構成部品を樹脂モー
ルドする工程で隣り合う半導体装置が分割される部分を
モールド樹脂で接続し、回路基板を分割して個々の半導
体装置にする工程において、ダイシングにより回路基板
を切断し、前記接続用モールド樹脂の一部は切断しない
で残しておく製造方法とする。A step of forming a plurality of circuit patterns on one circuit board, a step of mounting a semiconductor and circuit components, a step of resin-sealing the semiconductor, and a step of resin-molding the semiconductor and circuit components. In a method of manufacturing a semiconductor device having a step of dividing a circuit board into individual semiconductor devices, in a step of resin-molding a semiconductor and circuit components, a portion where adjacent semiconductor devices are divided is connected with a mold resin, In the step of dividing the circuit board into individual semiconductor devices, the circuit board is cut by dicing, and a part of the connection molding resin is left uncut.

【００１１】１枚の回路基板に複数の回路パターンを形
成する工程と、半導体および回路構成部品を搭載する工
程と、半導体を樹脂封止する工程と、半導体および回路
構成部品を樹脂モールドする工程と、回路基板を分割し
て個々の半導体装置にする工程を有する半導体装置の製
造方法において、半導体を樹脂封止する工程で隣り合う
半導体装置が分割される部分を半導体用封止樹脂で接続
し、半導体および回路構成部品を樹脂モールドする工程
で隣り合う半導体装置が分割される部分をモールド樹脂
で接続し、回路基板を分割して個々の半導体装置にする
工程において、ダイシングにより回路基板を切断し、前
記接続用半導体用封止樹脂と接続用モールド樹脂の積層
部の一部は切断しないで残しておく製造方法とする。A step of forming a plurality of circuit patterns on one circuit board, a step of mounting a semiconductor and circuit components, a step of resin-sealing the semiconductor, and a step of resin-molding the semiconductor and circuit components. In a method of manufacturing a semiconductor device having a step of dividing a circuit board into individual semiconductor devices, in a step of sealing a semiconductor with a resin, a portion where an adjacent semiconductor device is divided is connected with a semiconductor sealing resin, In the step of resin-molding the semiconductor and circuit components, the portions where adjacent semiconductor devices are divided are connected with mold resin, and in the process of dividing the circuit board into individual semiconductor devices, the circuit board is cut by dicing, The manufacturing method is to leave a part of the laminated portion of the sealing resin for the connection semiconductor and the molding resin for the connection without cutting.

【００１２】[0012]

【発明の実施の形態】図２〜図５は本発明を説明するた
めの工程毎の斜視図である。図２は回路基板１であり、
図３は半導体２を搭載してワイヤーボンディングした状
態である。図４は半導体を樹脂３で封止した状態であ
り、この後回路構成部品を搭載する。図５は回路基板１
の上下に搭載された構成部品をモールド樹脂５でモール
ドした状態である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2 to 5 are perspective views for each step for explaining the present invention. FIG. 2 is a circuit board 1,
FIG. 3 shows a state where the semiconductor 2 is mounted and wire-bonded. FIG. 4 shows a state in which the semiconductor is sealed with the resin 3, and thereafter, circuit components are mounted. FIG. 5 shows the circuit board 1
In this state, the components mounted above and below are molded with the molding resin 5.

【００１３】図６（Ａ）〜（Ｅ）は本発明の説明をする
ための工程毎の断面図である。（Ａ）は回路基板１であ
り、（Ｂ）は半導体２を搭載し樹脂３で封止した状態で
あり、図４に対応している。（Ｃ）は回路構成部品を搭
載した状態であり、（Ｄ）は樹脂５でモールドした状態
である。（Ｅ）は半導体装置間を回路基板１側からダイ
シングした状態である。溝６はダイシングによるもので
あり、封止樹脂３は切り離されずに残っている。ダイシ
ングは（C）の状態で行なうのも可能であり、その後樹
脂モールドすれば（Ｅ）の状態になる。（Ｅ）の状態で
は各半導体装置は封止樹脂３の薄肉部で接続されてい
る。半導体装置を回路基板等に実装する際に個々にブレ
ークして使用する。以下の例でも同様である。FIGS. 6A to 6E are cross-sectional views for each step for explaining the present invention. (A) shows a circuit board 1 and (B) shows a state in which a semiconductor 2 is mounted and sealed with a resin 3 and corresponds to FIG. (C) shows a state where the circuit components are mounted, and (D) shows a state where it is molded with the resin 5. (E) shows a state in which the semiconductor devices are diced from the circuit board 1 side. The groove 6 is formed by dicing, and the sealing resin 3 remains without being separated. The dicing can be performed in the state of (C), and then the state is changed to (E) by resin molding. In the state (E), each semiconductor device is connected by a thin portion of the sealing resin 3. The semiconductor devices are individually broken when mounted on a circuit board or the like. The same applies to the following examples.

【００１４】図７は本発明の他の実施形態であり断面図
である。半導体２の樹脂封止は個々に行ない、回路基板
１の切断部はモールド樹脂５で接続した構造である。樹
脂封止に封止枠を使用してないが、封止枠を使用する構
造でもよい。ダイシング後の各半導体装置はモールド樹
脂５の薄肉部で接続されている。FIG. 7 is a sectional view showing another embodiment of the present invention. The semiconductor 2 is sealed individually with resin, and the cut portions of the circuit board 1 are connected by a mold resin 5. Although a sealing frame is not used for resin sealing, a structure using a sealing frame may be used. Each semiconductor device after dicing is connected by a thin portion of the mold resin 5.

【００１５】図８は本発明の更に他の実施形態の断面図
である。封止樹脂３の接続部にも樹脂モールドしたもの
である。図８においてダイシングは封止樹脂３で止めて
あるが、モールド樹脂５まで到達させるか否かは構造お
よび製法上で自由にできるものである。本発明は図１
（Ｅ）のように余分な回路基板部１’を有するものでも
同様に実施することができる。FIG. 8 is a sectional view of still another embodiment of the present invention. The connection portion of the sealing resin 3 is also resin-molded. Although the dicing is stopped by the sealing resin 3 in FIG. 8, whether or not the dicing reaches the molding resin 5 can be freely determined in terms of structure and manufacturing method. The present invention is shown in FIG.
As in the case of (E), a device having an extra circuit board portion 1 'can be similarly implemented.

【００１６】以上の説明では１枚の回路基板に５個の半
導体を搭載した例であるが、大きな回路基板で半導体を
沢山搭載し、ダイシングで碁盤の目のように切断する場
合により有効な発明である。Although the above description is an example in which five semiconductors are mounted on one circuit board, the invention is more effective when a large number of semiconductors are mounted on a large circuit board and cut like a grid by dicing. It is.

【００１７】[0017]

【発明の効果】半導体装置完成後も使用するまでは個々
の半導体装置がブレークしやすい樹脂部で接続されてい
るので取り扱いが容易になった。According to the present invention, even after the semiconductor device is completed, the individual semiconductor devices are connected by a resin portion which is easily broken before use, so that the handling becomes easy.

【００１８】ブレークが回路基板のブレークでなく、封
止樹脂および／またはモールド樹脂の薄肉部なので回路
基板に応力をかけずにブレークできるようになった。Since the break is not a break of the circuit board but a thin portion of the sealing resin and / or the mold resin, the break can be performed without applying a stress to the circuit board.

【００１９】ダイシング時に余分な回路基板が飛び散る
ことが無く、ブレードを破損することが無くなった。よ
って、半導体装置を安価に製造することができるように
なった。No extra circuit board is scattered during dicing, and the blade is not damaged. Therefore, a semiconductor device can be manufactured at low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図１】従来技術による半導体装置製造方法の工程図FIG. 1 is a process diagram of a conventional semiconductor device manufacturing method.

【図２】本発明を説明するための工程の斜視図FIG. 2 is a perspective view of a process for explaining the present invention.

【図３】本発明を説明するための工程の斜視図FIG. 3 is a perspective view of a process for explaining the present invention.

【図４】本発明を説明するための工程の斜視図FIG. 4 is a perspective view of a process for explaining the present invention.

【図５】本発明を説明するための工程の斜視図FIG. 5 is a perspective view of a process for explaining the present invention.

【図６】本発明の説明をするための工程の断面図FIG. 6 is a sectional view of a step for explaining the present invention.

【図７】本発明の他の実施形態であり断面図FIG. 7 is a sectional view showing another embodiment of the present invention.

【図８】本発明の更に他の実施形態の断面図FIG. 8 is a sectional view of still another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 回路基板 １’ 余分な回路基板 ２ 半導体 ３ 封止樹脂 ４ 回路構成部品 ５ モールド樹脂 ６ 溝 DESCRIPTION OF SYMBOLS 1 Circuit board 1 'Extra circuit board 2 Semiconductor 3 Sealing resin 4 Circuit component 5 Mold resin 6 Groove

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 １枚の回路基板に複数の回路パターンを
形成し、半導体および回路構成部品を搭載後樹脂モール
ドして個々の半導体装置として分割する半導体装置にお
いて、分割前は隣り合う半導体装置が半導体用の封止樹
脂および／またはモールド樹脂で接続されていることを
特徴とする半導体装置。1. A semiconductor device in which a plurality of circuit patterns are formed on a single circuit board, and a semiconductor and circuit components are mounted thereon and then resin-molded to be divided into individual semiconductor devices. A semiconductor device characterized by being connected by a sealing resin and / or a mold resin for a semiconductor. 【請求項２】 １枚の回路基板に複数の回路パターンを
形成する工程と、半導体および回路構成部品を搭載する
工程と、半導体を樹脂封止する工程と、半導体および回
路構成部品を樹脂モールドする工程と、回路基板を分割
して個々の半導体装置にする工程を有する半導体装置の
製造方法において、半導体を樹脂封止する工程で隣り合
う半導体装置が分割される部分を半導体用封止樹脂で接
続し、回路基板を分割して個々の半導体装置にする工程
において、ダイシングにより回路基板を切断し、前記接
続用半導体用封止樹脂の一部は切断しないことを特徴と
する半導体装置の製造方法。2. A step of forming a plurality of circuit patterns on one circuit board, a step of mounting a semiconductor and circuit components, a step of resin-sealing the semiconductor, and a step of resin-molding the semiconductor and circuit components. In a method of manufacturing a semiconductor device having a step and a step of dividing a circuit board into individual semiconductor devices, a portion where an adjacent semiconductor device is divided in a step of sealing a semiconductor with a resin is connected with a semiconductor sealing resin. In the step of dividing the circuit board into individual semiconductor devices, the circuit board is cut by dicing, and a part of the connection semiconductor sealing resin is not cut. 【請求項３】 １枚の回路基板に複数の回路パターンを
形成する工程と、半導体および回路構成部品を搭載する
工程と、半導体を樹脂封止する工程と、半導体および回
路構成部品を樹脂モールドする工程と、回路基板を分割
して個々の半導体装置にする工程を有する半導体装置の
製造方法において、半導体および回路構成部品を樹脂モ
ールドする工程で隣り合う半導体装置が分割される部分
をモールド樹脂で接続し、回路基板を分割して個々の半
導体装置にする工程において、ダイシングにより回路基
板を切断し、前記接続用モールド樹脂の一部は切断しな
いことを特徴とする半導体装置の製造方法。3. A step of forming a plurality of circuit patterns on one circuit board, a step of mounting a semiconductor and a circuit component, a step of resin-sealing the semiconductor, and a step of resin-molding the semiconductor and the circuit component. In a method of manufacturing a semiconductor device having a process and a process of dividing a circuit board into individual semiconductor devices, a portion where adjacent semiconductor devices are divided in a process of resin-molding a semiconductor and circuit components is connected with a molding resin. In the step of dividing the circuit board into individual semiconductor devices, the circuit board is cut by dicing, and a part of the connection molding resin is not cut. 【請求項４】 １枚の回路基板に複数の回路パターンを
形成する工程と、半導体および回路構成部品を搭載する
工程と、半導体を樹脂封止する工程と、半導体および回
路構成部品を樹脂モールドする工程と、回路基板を分割
して個々の半導体装置にする工程を有する半導体装置の
製造方法において、半導体を樹脂封止する工程で隣り合
う半導体装置が分割される部分を半導体用封止樹脂で接
続し、半導体および回路構成部品を樹脂モールドする工
程で隣り合う半導体装置が分割される部分をモールド樹
脂で接続し、回路基板を分割して個々の半導体装置にす
る工程において、ダイシングにより回路基板を切断し、
前記接続用半導体用封止樹脂と接続用モールド樹脂の積
層部の一部は切断しないことを特徴とする半導体装置の
製造方法。4. A step of forming a plurality of circuit patterns on one circuit board, a step of mounting a semiconductor and circuit components, a step of resin-sealing the semiconductor, and a step of resin-molding the semiconductor and circuit components. In a method of manufacturing a semiconductor device having a step and a step of dividing a circuit board into individual semiconductor devices, a portion where an adjacent semiconductor device is divided in a step of sealing a semiconductor with a resin is connected with a semiconductor sealing resin. In a step of resin-molding a semiconductor and circuit components, a portion where adjacent semiconductor devices are divided is connected with a mold resin, and in a process of dividing the circuit board into individual semiconductor devices, the circuit board is cut by dicing. And
A method of manufacturing a semiconductor device, wherein a part of a laminated portion of the connection semiconductor sealing resin and the connection molding resin is not cut.
JP10223072A 1998-08-06 1998-08-06 Semiconductor device and its manufacture Pending JP2000058572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10223072A JP2000058572A (en) 1998-08-06 1998-08-06 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10223072A JP2000058572A (en) 1998-08-06 1998-08-06 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JP2000058572A true JP2000058572A (en) 2000-02-25

Family

ID=16792401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10223072A Pending JP2000058572A (en) 1998-08-06 1998-08-06 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JP2000058572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011060985A (en) * 2009-09-10 2011-03-24 Murata Mfg Co Ltd Method of manufacturing electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011060985A (en) * 2009-09-10 2011-03-24 Murata Mfg Co Ltd Method of manufacturing electronic component

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