JPH0424865B2 - - Google Patents
Info
- Publication number
- JPH0424865B2 JPH0424865B2 JP18069087A JP18069087A JPH0424865B2 JP H0424865 B2 JPH0424865 B2 JP H0424865B2 JP 18069087 A JP18069087 A JP 18069087A JP 18069087 A JP18069087 A JP 18069087A JP H0424865 B2 JPH0424865 B2 JP H0424865B2
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- connecting band
- width
- end surfaces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 description 11
- 238000004080 punching Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、樹脂封止型ダイオード、トランジス
タ、混成集積回路等の電気部品をリードフレーム
を使用して製造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing electrical components such as resin-sealed diodes, transistors, hybrid integrated circuits, etc. using lead frames.
樹脂封止型トランジスタを第５図に示すリード
フレーム１を使用して製作することは既に行われ
ている。第５図のリードフレーム１は１個のトラ
ンジスタに対して３本のリード２，３，４を有
し、各リード２，３，４は連結帯５によつて相互
に連結されていると共に、ダイバーと呼ばれる連
結細条６によつても相互に連結されている。各リ
ード２，３，４は第１の方向に延び、連結帯５及
び連結細条６は第１の方向に対して直角な第２の
方向に延びている。中央のリード線３には支持板
７が一体化され、この支持板７の上にトランジス
タを構成する半導体チツプ８が固着されている。
半導体チツプ８の下面のコレクタ電極は支持板７
を介してリード３に接続されている。半導体チツ
プ８の上面のエミツタ電極（図示せず）とリード
２の一端との間は内部リード９によつて接続さ
れ、ベース電極（図示せず）とリード４との間は
内部リード１０によつて接続されている。各リー
ド２，３，４の一端部、半導体チツプ８、支持板
７、及び各内部リード９，１０は破線で示す外囲
体としての樹脂封止体１１によつて一体化され
る。連結帯５及び連結細条６は樹脂封止体１１を
設けた後に点線１２，１３の部分で切断除去され
る。
A resin-sealed transistor has already been manufactured using the lead frame 1 shown in FIG. The lead frame 1 in FIG. 5 has three leads 2, 3, 4 for one transistor, and each lead 2, 3, 4 is interconnected by a connecting band 5. They are also interconnected by connecting strips 6 called divers. Each lead 2, 3, 4 extends in a first direction, and the connecting band 5 and connecting strip 6 extend in a second direction perpendicular to the first direction. A support plate 7 is integrated with the center lead wire 3, and a semiconductor chip 8 constituting a transistor is fixed onto the support plate 7.
The collector electrode on the lower surface of the semiconductor chip 8 is connected to the support plate 7.
It is connected to lead 3 via. The emitter electrode (not shown) on the top surface of the semiconductor chip 8 and one end of the lead 2 are connected by an internal lead 9, and the base electrode (not shown) and the lead 4 are connected by an internal lead 10. connected. One end of each lead 2, 3, 4, the semiconductor chip 8, the support plate 7, and each internal lead 9, 10 are integrated by a resin sealing body 11 as an envelope shown by a broken line. The connecting band 5 and the connecting strip 6 are cut and removed at the dotted lines 12 and 13 after the resin sealing body 11 is provided.
ところで、半導体装置の材料コストの低減を図
るために、本件出願人は、連結帯５を第５図の点
線１２に沿つて切断除去する代りに、点線１４で
示す部分で切断除去し、リード２，３，４の延長
部２ａ，３ａ，４ａを設けることを検討した。こ
の様に構成すると、連結帯５をリードの一部とし
て使用することができるので、リードフレーム１
の小型化が達成され、コストの低減が可能にな
る。
Incidentally, in order to reduce the material cost of the semiconductor device, the present applicant cut and removed the connecting band 5 along the dotted line 14 in FIG. 5 instead of cutting and removing it along the dotted line 14, and , 3, and 4 extension parts 2a, 3a, and 4a were considered. With this configuration, the connecting band 5 can be used as a part of the lead, so the lead frame 1
It is possible to achieve miniaturization and reduce costs.
しかし、各リード２，３，４の両側端面の延長
線である点線１４において正確に切断することに
困難を伴なつた。即ち、点線１３及び１４の切断
は、ブレス型を使用した打ち抜きにより行われる
が、打ち抜き位置の左右のずれが生じた。第６図
は右にずれた打ち抜き後のリード２の拡大図であ
る。この第６図から明らかな如く、リード２の本
来の部分と延長部２ａとの間に段差が生じる。こ
の結果、実効的なリード幅Ｌは、本来のリード幅
L1に段差の高さＨを加算したものになる。また、
プレス型の位置ずれが生じると、直線状の切断と
ならずに屈曲面を有する切断となるために段差の
部分に第７図に示す如くバリ１５が生じる。 However, it was difficult to accurately cut the leads 2, 3, and 4 along the dotted lines 14, which are extensions of both end surfaces. That is, although the cuts along the dotted lines 13 and 14 were performed by punching using a press die, the punching positions were shifted from left to right. FIG. 6 is an enlarged view of the lead 2 after punching shifted to the right. As is clear from FIG. 6, a step is created between the original portion of the lead 2 and the extended portion 2a. As a result, the effective lead width L is the original lead width
It is the sum of L 1 and the height H of the step. Also,
When the press die is misaligned, the cut is not a straight line but has a curved surface, so that burrs 15 are generated at the stepped portions as shown in FIG.
第６図に示す如くリード２の幅が実効的に大き
くなつたり、第７図に示す如くバリ１５が生じる
と、回路基板の貫通孔（スルーホール）にリード
２〜４を円滑に挿入することが不可能になつた。 When the width of the leads 2 becomes effectively large as shown in FIG. 6, or when burrs 15 occur as shown in FIG. 7, it is difficult to smoothly insert the leads 2 to 4 into the through holes of the circuit board. became impossible.
今、トランジスタを例にとつて説明したが、リ
ードフレームを使用する別の種々の電気部品にも
同様な問題がある。 Although the explanation has been made using a transistor as an example, similar problems exist in various other electrical components that use lead frames.
そこで、本発明の目的は、連結帯から良好なリ
ード延長部を容易に得る方法を提供することにあ
る。 SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for easily obtaining a good lead extension from a connecting band.
上記問題点を解決し、上記目的を達成するため
の本発明は、実施例を示す図面の符号を参照して
説明すると、少くなとも複数のリード２，３，４
とこの複数のリード２，３，４を相互に連結する
ための連結帯５とを備え、前記複数のリード２，
３，４が第１の方向に延びるように配置され、前
記連結帯５が前記第１の方向に対して直角な第２
の方向に延びるように配置されているリードフレ
ーム１を用意する工程と、前記リード２，３，４
に電気回路素子又は回路装置を接続し、前記電気
回路素子又は回路装置と前記リード２，３，４の
端部との外囲体によつて一体化する工程と、前記
リード２，３，４の延長部２ａ，３ａ，４ａを形
成するように前記連結帯５を切断する工程とを有
して電気部品を製造する方法において、前記リー
ド２，３，４の前記連結帯５の近傍領域の両側端
面に前記リード２，３，４の幅狭部１８が生じる
ように凹部１６，１７を予め設け、前記リード
２，３，４の前記延長部２ａ，３ａ，４ａを形成
する際に、前記延長部２ａ，３ａ，４ａの両側端
面２０ａ，２０ｂが前記幅狭部１８の両側端面１
８ａ，１８ｂの延長線と前記幅狭部１８に隣接す
る幅広部１９の両側端面１９ａ，１９ｂの延長線
との間に位置するように前記連結帯５を切断除去
することを特徴とする電気部品の製造方法に係わ
るものである。
To solve the above problems and achieve the above objects, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments.
and a connection band 5 for interconnecting the plurality of leads 2, 3, 4.
3 and 4 are arranged to extend in a first direction, and the connecting band 5 extends in a second direction perpendicular to the first direction.
a step of preparing a lead frame 1 arranged so as to extend in the direction of
a step of connecting an electric circuit element or circuit device to and integrating the electric circuit element or circuit device and the ends of the leads 2, 3, 4 by an outer envelope; and cutting the connecting band 5 to form extensions 2a, 3a, 4a of the leads 2, 3, 4 in the vicinity of the connecting band 5. Recesses 16 and 17 are provided in advance so that the narrow width portions 18 of the leads 2, 3, and 4 are formed on both end surfaces, and when forming the extension portions 2a, 3a, and 4a of the leads 2, 3, and 4, Both side end surfaces 20a, 20b of the extension portions 2a, 3a, 4a are the both side end surfaces 1 of the narrow width portion 18.
The electrical component is characterized in that the connecting band 5 is cut and removed so as to be located between an extension line of 8a, 18b and an extension line of both end surfaces 19a, 19b of the wide part 19 adjacent to the narrow part 18. This relates to the manufacturing method.
上記発明における凹部１６，１７は連結帯５の
切断時における位置ずれによるびバリの発生を阻
止する。即ち、連結帯５の切断位置が凹部１６，
１７の深さの範囲内にある限り、直線的な決断に
なり、バリが発生しない。また、リード延長部２
ａ，３ａ，４ａの両側端面２０ａ，２０ｂがリー
ドの幅広部１９の両側端面１９ａ，１９ｂの延長
線よりも外側に位置することを防ぐことができ
る。
The recesses 16 and 17 in the above invention prevent the occurrence of burrs due to misalignment when the connecting band 5 is cut. That is, the cutting position of the connecting band 5 is the recess 16,
As long as it is within the depth range of 17, the resolution will be straight and no burrs will occur. In addition, the lead extension part 2
It is possible to prevent the both side end surfaces 20a, 20b of the leads a, 3a, 4a from being located outside the extension line of the both side end surfaces 19a, 19b of the wide part 19 of the lead.
次に、第１図〜第４図を参照して本発明の実施
例に係わる樹脂封止型半導体装置の製造方法を説
明する。但し、第１図〜第４図において、符号１
〜１１，１３，１４で示すものは第５図で同一符
号で示すものと実質的に同一であるので、その説
明を省略する。第１図に示す本実施例のリードフ
レーム１においては、各板状リード２，３，４の
連結帯５の近傍領域の両側端面に凹部１６，１７
がそれぞれ設けられている。第２図及び第３図に
示す如くリード２を例にとつて説明すると、一対
の凹部１６，１７を設けた部分が幅狭部１８とな
り、これが幅広部１９に連続している。幅狭部１
８の両側端面１８ａ，１８ｂは、幅広部１９の両
側端面１９ａ，１９ｂよりも内側に位置してい
る。一対の凹部１６，１７は連結帯５と幅広部１
９との間に左右対称に設けられている。幅広部１
９の幅L1は1.0mm、幅狭部１８の幅L2は0.9mm、各
凹部１６，１７の深さＤはそれぞれ0.05mmであ
る。他のリード３，４の連結帯５の近傍部分もリ
ード２と全く同様に形成されている。
Next, a method for manufacturing a resin-sealed semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4. However, in Figures 1 to 4, the symbol 1
11, 13, and 14 are substantially the same as those indicated by the same reference numerals in FIG. 5, so their explanation will be omitted. In the lead frame 1 of this embodiment shown in FIG.
are provided for each. Taking the lead 2 as an example as shown in FIGS. 2 and 3, a portion provided with a pair of recesses 16 and 17 becomes a narrow portion 18, which is continuous with a wide portion 19. Narrow part 1
Both side end surfaces 18a and 18b of the wide portion 19 are located inside of both side end surfaces 19a and 19b of the wide portion 19. A pair of recesses 16 and 17 are connected to the connecting band 5 and the wide part 1.
9 and is provided symmetrically between the left and right sides. Wide part 1
The width L 1 of the groove 9 is 1.0 mm, the width L 2 of the narrow portion 18 is 0.9 mm, and the depth D of each of the recesses 16 and 17 is 0.05 mm. The portions of the other leads 3 and 4 near the connecting band 5 are also formed in exactly the same manner as the lead 2.
リードフレーム１に対する半導体チツプ８の固
着、内部リード９，１０の接続、トランスフアー
モールドによる樹脂封止体１１の形成が終了した
ら、第１図の点線１３，１４で示す位置をプレス
型に使用して打ち抜き切断し、連結帯５及び連結
細条６を除去し、第４図に示す樹脂封止型半導体
素子を得る。ここで重要なことは点線１４で示す
切断予定位置を幅狭部１８の両側端面１８ａ，１
８ｂの延長線と幅広部１９の両側端面１９ａ，１
９ｂの延長線との間に設定したことである。プレ
ス型による打ち抜き加工時のプレス型の連結帯５
の延びる方向（第２の方向）の位置ずれの公差を
Ｔとすれば、凹部１６，１７の深さＤを2Tに設
定し、点線１４で示す切断予定位置を凹部１６，
１７の深さＤの中間即ち幅狭部１８の両側端面１
８ａ，１８ｂの延長線と幅広部１９の両側端面１
９ａ，１９ｂの延長線との中間に設定することが
最も好ましい。 After fixing the semiconductor chip 8 to the lead frame 1, connecting the internal leads 9 and 10, and forming the resin sealing body 11 by transfer molding, use the positions indicated by dotted lines 13 and 14 in FIG. 1 as a press mold. Then, the connecting band 5 and the connecting strip 6 are removed to obtain a resin-sealed semiconductor element shown in FIG. 4. What is important here is that the planned cutting position indicated by the dotted line 14 is
8b and both end surfaces 19a, 1 of the wide portion 19
This is because it is set between the extension line of 9b. Connecting band 5 of press die during punching process using press die
If the tolerance for positional deviation in the extending direction (second direction) is T, then the depth D of the recesses 16, 17 is set to 2T, and the planned cutting position shown by the dotted line 14 is set to the recess 16, 17.
17, the middle of the depth D, that is, both side end surfaces 1 of the narrow portion 18
Extension lines of 8a and 18b and both end surfaces 1 of wide part 19
It is most preferable to set it midway between the extension lines of 9a and 19b.
凹部１６，１７のリード２，３，４の延びる方
向（第１の方向）の幅はプレス型の第１の方向の
位置ずれ公差以上（0.05mm以上）に設定されてい
る。従つて、プレス型が第１の方向に公差の範囲
でずれても、リードの幅広部１９が切断されるお
それはない。 The widths of the recesses 16 and 17 in the direction in which the leads 2, 3, and 4 extend (first direction) are set to be greater than or equal to the displacement tolerance of the press mold in the first direction (0.05 mm or greater). Therefore, even if the press die deviates in the first direction within the tolerance range, there is no risk of the wide portion 19 of the lead being cut.
なお、連結細条６の切断は段部が生じるように
行われているが、回路基板の貫通孔に挿入する部
分ではないので、何らの問題も生じない。 Note that although the connecting strip 6 is cut so as to produce a stepped portion, since this is not a portion to be inserted into a through hole of a circuit board, no problem arises.
第３図は第２図の点線１４で連結帯５を切断し
てリード延長部２ａを形成した状態を示す。この
リード延長部２ａ幅L3は、幅狭部１８の幅L2と
幅広部１９の幅L1との中間の0.95mmである。 FIG. 3 shows a state in which the connecting band 5 is cut along the dotted line 14 in FIG. 2 to form the lead extension portion 2a. The width L 3 of this lead extension portion 2a is 0.95 mm, which is between the width L 2 of the narrow portion 18 and the width L 1 of the wide portion 19.
第２図の点線１４で示す予定切断位置が左又は
右に最大でＤ／２＝0.025mmずれたとしても、延
長部２ａの両側端面２０ａ，２０ｂが幅広部１９
の両側端面１９ａ，１９ｂの延長線よりも外側に
位置せず、且つ幅狭部１８の両側端面１８ａ，１
８ｂの内側に位置しない。このため、延長部２ａ
を設けることによつてリード幅が実効的に増大す
ることはない。また、第６図に示すような屈曲面
を有する切断状態にならないので、バリが発生し
ない。換言すれば、±0.025mmのように比較的大き
な位置ずれ誤差を有するブレス型を使用して延長
部２ａ，３ａ，４ａを形成しても、直線状の切断
となるためバリが生じない。 Even if the planned cutting position indicated by the dotted line 14 in FIG.
is not located outside the extension line of both side end surfaces 19a, 19b, and both side end surfaces 18a, 1 of the narrow width portion 18
It is not located inside 8b. For this reason, the extension part 2a
The lead width is not effectively increased by providing the lead width. Furthermore, since the cut does not have a curved surface as shown in FIG. 6, burrs do not occur. In other words, even if the extensions 2a, 3a, 4a are formed using a press die having a relatively large positional deviation error of ±0.025 mm, no burrs will occur because the cuts will be straight.
従つて、回路基板の貫通孔に対して挿入しやす
いリードを容易に形成することができる。 Therefore, a lead that can be easily inserted into a through hole of a circuit board can be easily formed.
本発明は上述の実施例に限定されるものではな
く、例えば次の変形が可能なものである。
The present invention is not limited to the above-described embodiments, but can be modified as follows, for example.
(1) 凹部１６，１７の深さＤはプレス型による打
ち抜きの公差の２倍にすることが望ましいが、
リード２，３，４の幅狭部１８が必要な強度を
有する範囲において更に深くしてもよい。幅狭
部１８の幅L2が幅広部１９の幅L1の約1/2にな
るように凹部１６，１７を形成しても実用上差
し支えないことが確認されている。(1) It is desirable that the depth D of the recesses 16 and 17 be twice the tolerance of punching with a press die;
The narrow portions 18 of the leads 2, 3, and 4 may be made deeper as long as the narrow portions 18 have the necessary strength. It has been confirmed that there is no practical problem in forming the recesses 16 and 17 so that the width L 2 of the narrow portion 18 is approximately 1/2 of the width L 1 of the wide portion 19.
(2) 凹部１６，１７の位置は、リード２〜４の先
端部以外の強度を大きく保つために連結帯５に
隣接していることが望ましいが、連結帯５から
少し離れていても差し支えない。(2) The positions of the recesses 16 and 17 are preferably adjacent to the connecting band 5 in order to maintain high strength other than the tips of the leads 2 to 4, but they may be located a little apart from the connecting band 5. .
(3) 第８図に示す如く連結帯５がリード２の先端
部２１よりも少し上に配設されている場合にも
適用可能である。この場合には先端部２１にも
凹部２２，２３を設けることが望ましい。又、
一対の凹部１６，１７を非対称に形成してもよ
い。(3) It is also applicable to the case where the connecting band 5 is disposed slightly above the tip end 21 of the lead 2 as shown in FIG. In this case, it is desirable to provide the recesses 22 and 23 in the tip portion 21 as well. or,
The pair of recesses 16 and 17 may be formed asymmetrically.
(4) 凹部１６，１７の形状は平面形状で四角形に
限ることなく、多段形状又は三角形状等であつ
てもよい。(4) The shape of the recesses 16 and 17 is not limited to a rectangular planar shape, but may be a multi-stage shape, a triangular shape, or the like.
(5) トランジスタに限ることなく、混成集積回
路、整流器等にも適用可能である。(5) It is applicable not only to transistors but also to hybrid integrated circuits, rectifiers, etc.
上述から明らかな如く、本発明によれば連結帯
を使用してリード延長部を形成する際に切断位置
がずれても、リード幅の実効的な増大バリが生じ
ない。従つて、回路基板の貫通孔に挿入し易いリ
ードを容易に提供することができる。
As is clear from the above, according to the present invention, even if the cutting position is shifted when forming a lead extension portion using a connecting band, no burr will effectively increase the lead width. Therefore, it is possible to easily provide a lead that can be easily inserted into a through hole of a circuit board.
第１図は本発明の実施例に係わるリードフレー
ムに半導体チツプを取付けた状態を示す平面図、
第２図は第１図の一部を示す拡大平面図、第３図
は第２図の連結帯を切断した状態を示す平面図、
第４図は完成した半導体装置を示す平面図、第５
図は従来のリードフレームを示す平面図、第６図
は第５図のリードフレームに基づいて形成したリ
ードの一部を示す拡大平面図、第７図は第６図の
左側面図、第８図は変形例のリードフレームの一
部を示す平面図である。
１……リードフレーム、２，３，４……リー
ド、５……連結帯、１１……樹脂封止体、１６，
１７……凹部、１８……幅狭部、１９……幅広
部。
FIG. 1 is a plan view showing a state in which a semiconductor chip is attached to a lead frame according to an embodiment of the present invention;
FIG. 2 is an enlarged plan view showing a part of FIG. 1, FIG. 3 is a plan view showing a state in which the connecting band in FIG. 2 is cut,
Figure 4 is a plan view showing the completed semiconductor device, Figure 5 is a plan view showing the completed semiconductor device;
6 is an enlarged plan view showing a part of a lead formed based on the lead frame of FIG. 5, FIG. 7 is a left side view of FIG. 6, and FIG. 8 is a plan view showing a conventional lead frame. The figure is a plan view showing a part of a lead frame of a modified example. 1... Lead frame, 2, 3, 4... Lead, 5... Connecting band, 11... Resin sealing body, 16,
17... Concave portion, 18... Narrow portion, 19... Wide portion.
Claims (1)
数のリード２，３，４を相互に連結するための連
結帯５とを備え、前記複数のリード２，３，４が
第１の方向に延びるように配置され、前記連結帯
５が前記第１の方向に対して直角な第２の方向に
延びるように配置されているリードフレーム１を
用意する工程と、 前記リード２，３，４に電気回路素子又は回路
装置を接続し、前記電気回路素子又は回路装置と
前記リード２，３，４の端部とを外囲体によつて
一体化する工程と、 前記リード２，３，４の延長部２ａ，３ａ，４
ａを形成するように前記連結帯５を切断する工程
と を有して電気部品を製造する方法において、 前記リード２，３，４の前記連結帯５の近傍領
域の両側端面に前記リード２，３，４の幅狭部１
８が生じるように凹部１６，１７を予め設け、 前記リード２，３，４の前記延長部２ａ，３
ａ，４ａを形成する際に、前記延長部２ａ，３
ａ，４ａの両側端面２０ａ，２０ｂが前記幅狭部
１８の両側端面１８ａ，１８ｂの延長線と前記幅
狭部１８に隣接する幅広部１９の両側端面１９
ａ，１９ｂの延長線との間に位置するように前記
連結帯５を切断除去することを特徴とする電気部
品の製造方法。 ２ 前記リード２，３，４の両側端面の凹部１
６，１７は同一の深さに形成されたものである特
許請求の範囲第１項記載の電気部品の製造方法。 ３ 前記延長部２ａ，３ａ，４ａは、前記幅狭部
１８の幅L2と前記幅広部１９の幅L1との中間の
幅L3を有するものである特許請求の範囲第２項
記載の電気部品の製造方法。[Scope of Claims] 1. At least a plurality of leads 2, 3, 4 and a connecting band 5 for interconnecting the plurality of leads 2, 3, 4, wherein the plurality of leads 2, 3, 4 are connected to each other. providing a lead frame 1 arranged to extend in a first direction, the connecting band 5 being arranged to extend in a second direction perpendicular to the first direction; , 3, and 4, and integrating the electrical circuit element or circuit device and the ends of the leads 2, 3, and 4 by an envelope; , 3, 4 extensions 2a, 3a, 4
The method for manufacturing an electrical component includes the step of cutting the connecting band 5 so as to form a line a, wherein the leads 2, 3, 4 narrow part 1
recessed portions 16 and 17 are provided in advance so that 8 is formed, and the extension portions 2a and 3 of the leads 2, 3 and 4 are
When forming the extension parts 2a and 3a,
Both side end surfaces 20a, 20b of a, 4a are extension lines of both side end surfaces 18a, 18b of the narrow width portion 18, and both side end surfaces 19 of the wide portion 19 adjacent to the narrow width portion 18.
A method for manufacturing an electrical component, characterized in that the connecting band 5 is cut and removed so as to be located between the extension lines of a and 19b. 2 Recesses 1 on both end surfaces of the leads 2, 3, and 4
2. The method of manufacturing an electrical component according to claim 1, wherein 6 and 17 are formed at the same depth. 3. The extension portions 2a, 3a, 4a have a width L3 intermediate between the width L2 of the narrow portion 18 and the width L1 of the wide portion 19. Method of manufacturing electrical parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18069087A JPS6424449A (en) | 1987-07-20 | 1987-07-20 | Manufacture of electric component using lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18069087A JPS6424449A (en) | 1987-07-20 | 1987-07-20 | Manufacture of electric component using lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6424449A JPS6424449A (en) | 1989-01-26 |
| JPH0424865B2 true JPH0424865B2 (en) | 1992-04-28 |
Family
ID=16087603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18069087A Granted JPS6424449A (en) | 1987-07-20 | 1987-07-20 | Manufacture of electric component using lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6424449A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009147032A (en) | 2007-12-13 | 2009-07-02 | Panasonic Corp | Semiconductor device, and optical pickup device |
-
1987
- 1987-07-20 JP JP18069087A patent/JPS6424449A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6424449A (en) | 1989-01-26 |
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