JPS62147932U - - Google Patents
Info
- Publication number
- JPS62147932U JPS62147932U JP1915087U JP1915087U JPS62147932U JP S62147932 U JPS62147932 U JP S62147932U JP 1915087 U JP1915087 U JP 1915087U JP 1915087 U JP1915087 U JP 1915087U JP S62147932 U JPS62147932 U JP S62147932U
- Authority
- JP
- Japan
- Prior art keywords
- controlled oscillator
- frequency
- signal
- voltage controlled
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000035945 sensitivity Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は典型的なフエーズロツク・ループ回路
の概略回路図、第２図及び第３図はその説明グラ
フ図、第４図は本考案の一般的構成を示す回路図
、第５図は本考案の一実施例回路図である。図で
２２はデジタル対アナログ変換器を示す。
FIG. 1 is a schematic circuit diagram of a typical phase lock loop circuit, FIGS. 2 and 3 are explanatory graphs thereof, FIG. 4 is a circuit diagram showing the general configuration of the present invention, and FIG. 5 is a circuit diagram of the present invention. FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, 22 indicates a digital-to-analog converter.
Claims (1)
受けるプログラマブル分周器、該分周器の出力信
号と基準信号とを比較しその出力を該電圧制御発
振器の制御入力に与える位相比較器を備えたフエ
ーズロツク・ループにおいて、該プログラマブル
位相比較器の分周率を定めるデジタル・データの
少なくとも一部を受け、該分周率に対応した電圧
制御発振器周波数を実質的に与えるアナログ信号
を該電圧制御発振器に与えるデジタル対アナログ
変換器を設け、該電圧制御発振器の変調感度を小
にしてその出力周波数信号のノイズを軽減するよ
うに構成したことを特徴とするフエーズロツク・
ループ。 A voltage controlled oscillator, a programmable frequency divider that receives a portion of its output frequency signal, and a phase comparator that compares the output signal of the frequency divider with a reference signal and provides the output to the control input of the voltage controlled oscillator. A phase lock loop receives at least a portion of the digital data defining a frequency division ratio of the programmable phase comparator and provides an analog signal to the voltage controlled oscillator that substantially provides a voltage controlled oscillator frequency corresponding to the frequency division ratio. A phase-lock device comprising: a digital-to-analog converter to reduce the noise of the output frequency signal by reducing the modulation sensitivity of the voltage-controlled oscillator;
loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1915087U JPS62147932U (en) | 1987-02-12 | 1987-02-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1915087U JPS62147932U (en) | 1987-02-12 | 1987-02-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62147932U true JPS62147932U (en) | 1987-09-18 |
Family
ID=30813488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1915087U Pending JPS62147932U (en) | 1987-02-12 | 1987-02-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62147932U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396655A (en) * | 1977-02-03 | 1978-08-24 | Marukon Denshi Kk | Pll synthesizer |
| JPS53127255A (en) * | 1977-04-13 | 1978-11-07 | Torio Kk | Phase lock loop circuit |
| JPS5428557A (en) * | 1977-08-05 | 1979-03-03 | Pioneer Electronic Corp | Frequency synthesizer |
-
1987
- 1987-02-12 JP JP1915087U patent/JPS62147932U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396655A (en) * | 1977-02-03 | 1978-08-24 | Marukon Denshi Kk | Pll synthesizer |
| JPS53127255A (en) * | 1977-04-13 | 1978-11-07 | Torio Kk | Phase lock loop circuit |
| JPS5428557A (en) * | 1977-08-05 | 1979-03-03 | Pioneer Electronic Corp | Frequency synthesizer |