JPS62147754A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62147754A JPS62147754A JP60288802A JP28880285A JPS62147754A JP S62147754 A JPS62147754 A JP S62147754A JP 60288802 A JP60288802 A JP 60288802A JP 28880285 A JP28880285 A JP 28880285A JP S62147754 A JPS62147754 A JP S62147754A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- pad
- film
- aluminum
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は耐湿性にすぐれた信頼性の高いボンディング用
パッド部を備えた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having a highly reliable bonding pad portion with excellent moisture resistance.
（従来の技術）
従来の半導体装置し言、ボンディング用パッド部に外部
引ｔＨＬ用細線導体をボンディングした後そのままの伏
Ｘμでパッケージに実裟される。すなわち、絶縁保護喚
上に開口されたポンディング用パラド部は外部引出し用
細線導体の周囲に露出面を残したｔ−まパッケージ内に
封入される０（発明が解決しようとする問題点）
しかしながら、このような実装構造の半導体装置は使用
中ボンディング用パッド部材が変質または消失するなど
信頼性上きわめて重大な障害をしばしば起こす。通常、
半導体装置の絶縁保護膜にはシリコン酸化膜（ＳｉＯｚ
）またけプラズマ窒化膜（８ｉ３Ｎ４）とリン硅酸ガラ
ス（ＰＳＧ）との２組構のものが、また、ボンディング
用パッド部材にはアルミニウム金属が多く用いられるが
、このパッド部材の変質または消失はパッケージ内への
浸水によって生じる。すなわち、この障害はパッケージ
内に侵入した水分がアルミ材を直接侵かして水酸化物を
形成せしめるか、または絶縁保護膜に含まれるナトリウ
ム、塩素などの不純物イオミなどのバット部材を溶解す
ることによって生じるものと推定されている。この障害
の発生は特に樹脂封止型のものに多く半導体装置の機能
を全く失わしめる。(Prior Art) In a conventional semiconductor device, after bonding an external thin line conductor for THL to a bonding pad portion, the semiconductor device is assembled into a package with the same shape as Xμ. That is, the padding pad portion opened for insulation protection is enclosed in a package that leaves an exposed surface around the thin wire conductor for external extraction (a problem to be solved by the invention). Semiconductor devices having such a mounting structure often suffer from extremely serious failures in terms of reliability, such as deterioration or disappearance of bonding pad members during use. usually,
Silicon oxide film (SiOz) is used as an insulating protective film for semiconductor devices.
) A two-piece structure consisting of a plasma nitride film (8i3N4) and a phosphosilicate glass (PSG) is used, and aluminum metal is often used for bonding pad members, but deterioration or loss of this pad member may occur. Caused by water seeping into the package. In other words, this failure is caused by moisture entering the package directly attacking the aluminum material and forming hydroxide, or by dissolving impurity ions such as sodium and chlorine contained in the insulating protective film into the batt material. It is estimated that this is caused by This failure is particularly common in resin-sealed semiconductor devices, causing the semiconductor device to completely lose its functionality.
（発明の目的）
本発明の目的は、上記の情況に鑑み、ボンディング用パ
ッド部の耐湿性を改善した半導体装置およびその製造方
法を提供することである。(Object of the Invention) In view of the above circumstances, an object of the present invention is to provide a semiconductor device with improved moisture resistance of a bonding pad portion and a method for manufacturing the same.
（発明の構成）
本発明の半導体装置は、半導体基板と、前記半導体基板
上の絶縁保護膜に開口されるボンディング用パッド部と
、前記ボンディング用パッド部とボンディング接続する
外部引出し用細線導体と、前記外部引出し用細線導体の
ボンディング接続領域を除くパッド部の格出面を被覆す
る前記パッド部材の不動態膜とを備えることを含む。(Structure of the Invention) A semiconductor device of the present invention includes a semiconductor substrate, a bonding pad portion opened in an insulating protective film on the semiconductor substrate, and a thin wire conductor for external extraction bonded to the bonding pad portion. and a passive film of the pad member that covers the projecting surface of the pad portion except for the bonding connection area of the thin wire conductor for external extraction.
また、本発明の半導体装置の製造方法は、半導体基板上
の絶縁保護膜にボンディング用アルミパッド部を開口す
る工程と、前記アルミパッド部に外部引出し用細線導体
を接続するボンディング工程と、前記ボンディング工程
終了後半導体基板全体を過酸化水素または濃硝酸の溶液
内に浸漬するアルミ不動態膜形成工程とを含む。Further, the method for manufacturing a semiconductor device of the present invention includes a step of opening an aluminum pad portion for bonding in an insulating protective film on a semiconductor substrate, a bonding step of connecting a thin wire conductor for external lead to the aluminum pad portion, and a step of opening an aluminum pad portion for bonding in an insulating protective film on a semiconductor substrate; After the process is completed, the entire semiconductor substrate is immersed in a solution of hydrogen peroxide or concentrated nitric acid to form an aluminum passive film.
（問題点を解決するための手段）
す斤わち、本発明によれば、ボンディング用パッド部の
露出面にはそのパッド部材の不動態から成る薄い安定膜
が予かしめ形成されパッケージ実装される。特にアルミ
パッド部の場合には、パッケージ実装に先立ちボンディ
ング終了後化学溶液中に浸漬してパッド部表面に薄いア
ルミナ（Ａ１２０３）膜を形成せしめる。(Means for Solving the Problems) According to the present invention, a thin stable film made of the passive state of the pad member is pre-crimped on the exposed surface of the bonding pad portion, and the package is mounted. . In particular, in the case of an aluminum pad part, prior to package mounting, after bonding is completed, it is immersed in a chemical solution to form a thin alumina (A1203) film on the surface of the pad part.
（作用）
金属の不動頭は常態よりも化学的にきわめて安定な貴金
属性を帯びるので、この膜で被覆されたパッド部の露出
面は実質上絶縁保護膜２同等の耐湿性を以って保轄され
る。以下図面を参照して本発明の詳細な説明する。(Function) Since the fixed head of the metal has noble metal properties that are chemically much more stable than in the normal state, the exposed surface of the pad portion covered with this film is maintained with moisture resistance substantially equivalent to that of the insulating protective film 2. be under the control of The present invention will be described in detail below with reference to the drawings.
（実施例）
第１図は本発明の一実施例を示す部分斜視図である。本
実施例ではアルミパッド部の基１合が例示され、半導体
基板１と、絶縁保護膜２と、ボンディング用パッド部３
と、外部引出し用細線導体４と、パッド部３０譚出面を
被覆するよう形成されたアルミナ不動態膜５とを含む０
ここでは理解を容易にする目的で不動態膜５には特に／
・ッチングが施されている。(Embodiment) FIG. 1 is a partial perspective view showing an embodiment of the present invention. In this embodiment, a base 1 of the aluminum pad part is illustrated, and includes a semiconductor substrate 1, an insulating protective film 2, and a bonding pad part 3.
, a thin wire conductor 4 for external lead-out, and an alumina passive film 5 formed to cover the exposed surface of the pad portion 30.
Here, for the purpose of easy understanding, the passive film 5 is particularly
- Has been etched.
また、第２図は上記実施例を線Ａ−Ａ’に沿い縦方向に
切断した場合の断面図で、パッド部３の構造を明確に示
したものである０ここで６はアルミ配線導体を示してい
る。FIG. 2 is a cross-sectional view of the above embodiment taken along the line A-A' in the vertical direction, clearly showing the structure of the pad portion 3.0 Here, 6 indicates an aluminum wiring conductor. It shows.
このアルミナ不動態膜５はつぎの手順によって形成され
る。すなわち、外部引出し用細線導体４をボンディング
した後、濃塵２０〜３５重量係からなる温度１０〜３０
℃の過酸化水素溶液内に５〜１０分間浸漬するか、また
は同じ温度の６０〜７０％濃度の濃硝酸溶液内に数秒間
浸す。これはり−ド・フレームに搭載したままでよい。This alumina passive film 5 is formed by the following procedure. That is, after bonding the thin wire conductor 4 for external drawing, the temperature is 10 to 30% with a concentration of dust of 20 to 35% by weight.
5-10 minutes in a hydrogen peroxide solution at 0.degree. C. or for a few seconds in a 60-70% concentrated nitric acid solution at the same temperature. This can be left mounted on the board frame.
この化学的処理によってアルミパッド部３の露出面には
厚さ０．０５〜０．１５ ｔｔｍの緻密なアルミナ（Ａ
１２０３ ）不動態膜５が容易に形成されるＱこの膜質
は緻密であり耐水、耐酸および耐熱の化学的にきわめて
安定しているので、アルミパッド部３の露出面に実質上
絶禄保誇膜が存在するよう作用し、アルミパッド部３の
耐湿性を顕著に改善する。Through this chemical treatment, the exposed surface of the aluminum pad portion 3 is coated with dense alumina (A
1203) Passive film 5 is easily formed Q: This film quality is dense and extremely chemically stable in terms of water resistance, acid resistance, and heat resistance, so it forms a virtually impervious film on the exposed surface of the aluminum pad portion 3. The moisture resistance of the aluminum pad portion 3 is significantly improved.
（発明の効果）
以上詳細に説明したように、本発明半導体装置はボンデ
ィング用パッド部の露出面が不動態膜で被覆され絶縁保
膿膜と同等以上の耐湿性で保護されているので、浸水に
因るパッド部材の変質または消失などの重大事故の発生
は見金属防止される、また、不動態膜の形成は簡単な化
学処理によって行ない得るので、耐湿性にすぐれた信頼
性高き半導体裂溝を鍍わめて容易に提供し得る。(Effects of the Invention) As explained in detail above, in the semiconductor device of the present invention, the exposed surface of the bonding pad portion is covered with a passive film and protected with moisture resistance equal to or higher than that of an insulating impulsion film. The occurrence of serious accidents such as deterioration or disappearance of pad members due to metallization can be prevented, and since the formation of a passive film can be performed by a simple chemical treatment, it is possible to create a highly reliable semiconductor groove with excellent moisture resistance. can be provided very easily.
第１図は本発明の一実施例を示す部分斜視図、第２図は
上記実施例を線Ａ−Ａ’に沿い縦方向に切断（、た場合
の断面図である。
１・・・・・半纒体基板、２・・・・Ｐ、縁保き膜、３
川・・ボンディング用パッド部、４・・・・・外部引出
し用細線導体、５・・・・不動態膜（アルミナ）、６・
・、・・・・ア＋”＋１Fig. 1 is a partial perspective view showing one embodiment of the present invention, and Fig. 2 is a cross-sectional view of the above embodiment cut vertically along line A-A'.・Semi-circular substrate, 2...P, edge protection film, 3
River...Bonding pad part, 4...Fine wire conductor for external extraction, 5...Passive film (alumina), 6...
・・・・・A+”+1
Claims (4)
開口されるボンディング用パッド部と、前記ボンディン
グ用パッド部とボンディング接続する外部引出し用細線
導体と、前記外部引出し用細線導体のボンディング接続
領域を除くパッド部の露出面を被覆する前記パッド部材
の不動態膜とを備えることを特徴とする半導体装置。(1) Bonding connection between a semiconductor substrate, a bonding pad portion opened in an insulating protective film on the semiconductor substrate, a thin wire conductor for external lead-out that is bonded to the bonding pad portion, and the thin wire conductor for external lead-out. A semiconductor device comprising: a passivation film of the pad member that covers the exposed surface of the pad portion except for the region.
属から成ることを特徴とする特許請求の範囲第（１）項
記載の半導体装置。(2) The semiconductor device according to claim (1), wherein the bonding pad member is made of aluminum metal.
ミパッド部を開口する工程と、前記アルミパッド部に外
部引出し用細線導体を接続するボンディング工程と、前
記ボンディング工程終了後半導体基板全体を過酸化水素
溶液内に浸漬するアルミ不動態膜形成工程とを含むこと
を特徴とする半導体装置の製造方法。(3) A process of opening an aluminum pad part for bonding in an insulating protective film on a semiconductor substrate, a bonding process of connecting a thin wire conductor for external extraction to the aluminum pad part, and a process of overoxidizing the entire semiconductor substrate after the bonding process is completed. 1. A method for manufacturing a semiconductor device, comprising the step of forming an aluminum passive film by immersing it in a hydrogen solution.
ミパッド部を開口する工程と、前記アルミパッド部に外
部引出し用細線導体を接続するボンディング工程と、前
記ボンディング工程終了後半導体基板全体を濃硝酸溶液
内に浸漬するアルミ不動態膜形成工程とを含むことを特
徴とする半導体装置の製造方法。(4) A process of opening an aluminum pad part for bonding in the insulating protective film on the semiconductor substrate, a bonding process of connecting a thin wire conductor for external lead to the aluminum pad part, and a process of cleaning the entire semiconductor substrate with concentrated nitric acid after the bonding process is completed. 1. A method for manufacturing a semiconductor device, comprising the step of forming an aluminum passive film by immersing it in a solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288802A JPS62147754A (en) | 1985-12-20 | 1985-12-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288802A JPS62147754A (en) | 1985-12-20 | 1985-12-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62147754A true JPS62147754A (en) | 1987-07-01 |
Family
ID=17734918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60288802A Pending JPS62147754A (en) | 1985-12-20 | 1985-12-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62147754A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5565378A (en) * | 1992-02-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution |
-
1985
- 1985-12-20 JP JP60288802A patent/JPS62147754A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5565378A (en) * | 1992-02-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution |
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