JPS6214106B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a junction field effect transistor.

FIG. 1 shows a partial cross-sectional schematic diagram of a conventional junction field effect transistor having a structure in which the bottom and side surfaces of an island region are separated by an insulator. In Figure 1, 1 is a silicon substrate, 2 is an insulator, 3 is, for example, an N-type silicon region, 4 is an N ⁺ type silicon region for making ohmic contact between the source or drain region and metal wiring, and 5 is a gate. This region is of the opposite conductivity type to 3, that is, it is a P-type silicon region.

Note that metal wiring is omitted in FIG. 1. 1st
In the figure, if the source and drain electrodes are taken out from the N ⁺ type silicon region 4 and the gate electrode is taken out from the P type silicon region 5 using metal wiring, for example, aluminum, the bottom and side surfaces of the island regions are separated by an insulating material. It becomes a junction field effect transistor.

FIG. 2 shows, in order of steps, a method for manufacturing the insulation isolation structure in the conventional insulation isolation type junction field effect transistor shown in FIG. First, a P-type silicon layer 11 is formed on the main surface of an N-type silicon substrate 1 (FIG. 1A), and an N-type silicon layer 3 is further formed on that surface (FIG. 2B). Next, a nitride film ₁₂ , which is a _hydrofluoric acid-resistant film, is selectively deposited on the surface only on the island region 14 (FIG. 3C). Next, the substrate 15 is immersed in a hydrofluoric acid solution, and anodic treatment is performed while applying a positive voltage to the substrate 15 and irradiating it with light. Then, the silicon becomes porous from the separation region 13 of the N-type silicon layer 3 exposed to the hydrofluoric acid solution toward the inside of the substrate 15. Porousness is P
When reaching the P-type silicon layer 11, the porosity progresses within the P-type silicon layer 11, and eventually the entire P-type silicon layer 11 becomes porous. Therefore, as shown in FIG. D, the island region 17 made of the N-type silicon layer 3 has a structure in which the bottom and side surfaces are surrounded by the porous silicon 16. When the substrate 18 is heat-treated in an oxidizing atmosphere, the porous silicon 16 is easily oxidized and becomes the insulator 2. If the nitride film 12 is then removed, an insulating isolation structure as shown in FIG. 2E is obtained. Then,
The insulated junction type field effect transistor shown in FIG. 1 can be obtained by performing a normal semiconductor device manufacturing method.

In the conventional isolated junction field effect transistor shown in FIG. 1, the entire bottom surface of the island region must be made porous. In a typical junction field effect transistor, the size of the island region is 300 to 500 μm square.

As the island area becomes larger, the time required to make it porous increases in proportion to the size of the island, and for the above-mentioned island area of 300 to 500 μm square, the time required to make it porous is 20 to 30 minutes.

As the porosity formation time increases, the nitride film, which is a hydrofluoric acid-resistant film, also needs to be 3000 Å or more thick. However, if the thickness of the nitride film exceeds 3000 Å, the silicon substrate may warp or crack.

Moreover, when the porous formation time becomes longer, strain rapidly occurs in the island region after oxidizing the above-mentioned porous silicon. FIG. 3 shows the relationship between the porosity formation time and the level difference in the island region after oxidation. When the porous formation time exceeds 10 minutes, the level difference in the island region increases rapidly, and the strain in the island region also increases rapidly. If the step difference in the island region becomes large, it is inconvenient in the semiconductor device manufacturing process, such as making microfabrication difficult in the photo-etching process or causing disconnection of the aluminum wiring. Also, as the strain increases,
This adversely affects electrical characteristics, such as a decrease in source-drain breakdown voltage and gate breakdown voltage, or an increase in gate leakage current.

As mentioned above, in the conventional isolated junction field effect transistor, the size of the island region is
Since it is 300~500μm square, the porous formation time is 20~
The duration was 30 minutes, and the above-mentioned drawbacks occurred.

The present invention provides a method for manufacturing an insulated junction field effect transistor without changing the area of the island region, that is, having the same mutual conductance as in the prior art, and without the above-mentioned drawbacks of the prior art.

In other words, in an isolated junction field effect transistor having the same island area as a conventional one, the bottom and side surfaces of the island region can be made porous in less than 1/5 of the conventional porous formation time, for example, 3 minutes. The present invention provides an isolated type junction field effect transistor that can be used as an insulated junction field effect transistor.

Therefore, according to the present invention, the thickness of the nitride film, which is a hydrofluoric acid-resistant film, is sufficient to be about 1000 Å, and warpage of the silicon substrate or cracking of the silicon substrate does not occur. Furthermore, the level difference in the island region is about 4000 Å, and no problem occurs in the manufacturing process of the semiconductor device. Furthermore, almost no distortion occurs in the island region, and the electrical characteristics are significantly improved.

A method for manufacturing a junction field effect transistor according to the present invention includes a method for manufacturing an insulating type junction field effect transistor in which the bottom and side surfaces of an island region are surrounded by an insulator, in which each lattice of the junction field effect transistor is The semiconductor layer of the first conductivity type formed on the bottom surface of the island region of the junction field effect transistor is transformed into a porous silicon layer by anodization from at least one of the invalid gate regions that are lattice points of the shaped gate. and a step of changing the porous silicon layer into an insulator.

A detailed explanation will be given below using an insulated junction type field effect transistor obtained by a method according to an embodiment of the present invention. FIG. 4 is a surface pattern diagram of a conventional isolation type junction field effect transistor. The aluminum wiring is omitted in the figure. Here 1
Reference numerals 9 and 20 are island regions made of N-type silicon layers, which are source S and drain D regions, respectively. Numerals 21 and 22 are N ⁺ type silicon regions for making ohmic contact with the source and drain regions, and 23 is a P type silicon region serving as a gate region. As shown in FIG. 4, the source S region 19 and the drain D region 20 are vertically and horizontally opposed to each other with the gate region 23 in between. Therefore, the gate region 23
It can be seen that the channel region functions effectively as a channel region. This gate region 23 is called an effective gate region. However, the upper, lower, left, and right sides of the hatched area 24 are effective gate regions, and the source or drain regions face each other in the diagonal direction.
4 does not work as a channel area. This shaded area 24 is referred to as an invalid gate area.

The present invention utilizes the above-mentioned ineffective gate region 24 as a window for making it porous. Therefore, the effective gate region 23 has the same area as the conventional one, and the gate width is exactly the same as the conventional one. Therefore, the same mutual conductance as before can be obtained.

FIG. 5 shows a partial cross-sectional model diagram of an example of an insulation-separated field effect transistor obtained by the method of manufacturing a junction field effect transistor of the present invention.
The aluminum wiring is omitted here. 31 is, for example, an N-type silicon substrate, and 32 is an insulator formed by oxidizing porous silicon. 33 is an island region made of an N-type silicon layer, and 34 and 35 are N ⁺ type silicon regions of the source S and drain D regions, respectively. 36 is P which becomes the gate region
It is a shaped silicon area. When the nitride film 12 in the isolation region (13 in FIG. 2) is opened, the nitride film is opened at the same time, and the ineffective gate region 24 is made porous at the same time as the isolation region in the subsequent porous process. The structure shown in FIG. 5 is obtained.

FIG. 6 shows a surface pattern diagram of one embodiment shown in FIG. 5. Here, 37 is an island region made of an N-type silicon layer, and 39 indicates a part of the island region 37. 38 is a separation area. In the conventional insulated junction type field effect transistor, the length of one side of the bottom surface of the island region 37 to be made porous is B in FIG. 6, and as described above, B=
It was 300 to 500 μm. However, in the isolated junction field effect transistor obtained by the present invention, the lattice point 2 of the gate region within the island region 37
4 (ineffective gate region) has a porous window in island region 3
A large number of them are provided in 7, and porous formation progresses simultaneously from the surface of the isolation region 38 and from the surface of the invalid gate region 24. Therefore, in order to make the entire bottom surface of the island region 37 porous, it is sufficient to make the bottom surface porous by the length of A in FIG. The value of A is approximately 20 μm in this embodiment. Therefore, a porous formation time of about 3 minutes is sufficient. Therefore, a thickness of 1000 Å for the nitride film, which serves as a mask for creating porosity, is sufficient, and the silicon substrate will not warp or crack, and the step difference in the island region is only about 4000 Å, making it ideal for semiconductor device manufacturing processes and electrical The effect on characteristics is also hardly a problem.

In the above description of the embodiment, drawings in which aluminum electrodes are omitted are used, but the gate electrodes are formed by providing an aluminum wiring layer on the surface of the gate diffusion layer.

As described above, in the method for manufacturing a junction field effect transistor of the present invention, a porous window is provided in the ineffective gate region, which is a lattice point of the gate region in the island region, and the surface of the ineffective gate region and the separation region is Since the porous state is progressed from the beginning, the time required to make the entire bottom surface of the island region porous is determined by the interval between the invalid gate regions, and is less than 1/5 of the conventional time. Furthermore, in the present invention, the size of the island region 37 is independent of the porous formation time, so the size of the island region 37 can be arbitrarily increased even with the same porous formation time.

As the porous formation time is less than 1/5 of the conventional time, the above-mentioned The drawbacks of the conventional method cannot occur.

In the embodiment of the present invention described above, a porous window is provided at the lattice points of the gate region, but even if this window is larger than the invalid gate region (for example, the region within the dotted line 40 in FIG. 6), Alternatively, even if it is made smaller, the effects of the present invention are not impaired. Further, the effects of the present invention can be obtained without providing porous windows at all of the lattice points as long as a porous window is provided at at least one lattice point within the island region.

Further, as another embodiment of the present invention, the silicon substrate at the lattice points is replaced with a P-type silicon layer (1 in FIG. 2).
A similar effect can be obtained by etching until reaching 1) and then making it porous.

Furthermore, the present invention is not limited to a single isolated type junction field effect transistor, but is also applicable to ICs and
It is clear that the present invention can also be applied to isolated junction field effect transistors in integrated circuits such as LSIs.

[Brief explanation of the drawing]

Figure 1 is a partial cross-sectional model diagram of a conventional junction field effect transistor, Figures 2 A to E are diagrams for explaining the manufacturing method of the transistor shown in Figure 1, and Figure 3 is the porous formation time. Diagram showing the relationship between and level difference, 4th
The figure is a surface pattern diagram of a conventional junction field effect transistor, Figure 5 is a partial cross-sectional model diagram of a junction field transistor according to an embodiment of the present invention, and Figure 6 is a surface pattern of the embodiment shown in Figure 5. It is a pattern diagram. 31...Silicon substrate, 32...Insulator, 33
... Island region, 34 ... Source region, 35 ... Drain region, 36 ... Gate region, 24 ... Invalid gate region.

Claims (1)

[Claims] 1. When manufacturing an isolation type junction field effect transistor in which the bottom and side surfaces of the island region are surrounded by an insulator, at least one of the ineffective gate regions which is a lattice point of each lattice gate of the junction field effect transistor is manufactured. A step of changing the first conductivity type semiconductor layer formed on the bottom surface of the island region of the junction field effect transistor into a porous silicon layer by anodizing, and converting the porous silicon layer to an insulator. 1. A method for manufacturing a junction field effect transistor, comprising the step of: