JPH0587016B2 - - Google Patents
Info
- Publication number
- JPH0587016B2 JPH0587016B2 JP61071129A JP7112986A JPH0587016B2 JP H0587016 B2 JPH0587016 B2 JP H0587016B2 JP 61071129 A JP61071129 A JP 61071129A JP 7112986 A JP7112986 A JP 7112986A JP H0587016 B2 JPH0587016 B2 JP H0587016B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- thermal oxide
- island region
- forming
- crystal defect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000007547 defect Effects 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 24
- 238000009792 diffusion process Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は半導体装置の製造方法に関し、特にコ
ンタクト部の形成に改良を施したものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and in particular, improves the formation of a contact portion.
（従来の技術）
従来、半導体装置を例えば第２図ａ〜ｃに示す
如く形成されている。(Prior Art) Conventionally, semiconductor devices have been formed as shown in FIGS. 2a to 2c, for example.
まず、例えばＮ型のシリコン基板１の表面にフ
イールド酸化膜２を形成する。つづいて、このフ
イールド酸化膜２で囲まれた前記基板１の島領域
３上に第１の熱酸化膜４を形成する（第２図ａ図
示）。なお、同図ａにおいて、５（点部分）は結
晶欠陥層である。次いで、前記第１の熱酸化膜４
を通して前記島領域３にBF2をイオン注入し、P+
型の拡散層６を形成する（第２図ｂ図示）。更に、
全面に層間絶縁膜７を形成した後、前記拡散層６
上の層間絶縁膜７を選択的に開孔してコンタクト
ホール８を形成する。この後、このコンタクトホ
ール８に取出し配線９を形成して半導体装置を製
造する（第２図ｃ図示）。 First, a field oxide film 2 is formed on the surface of an N-type silicon substrate 1, for example. Subsequently, a first thermal oxide film 4 is formed on the island region 3 of the substrate 1 surrounded by the field oxide film 2 (as shown in FIG. 2A). In addition, in the same figure a, 5 (dot part) is a crystal defect layer. Next, the first thermal oxide film 4
BF 2 is ion-implanted into the island region 3 through P +
A mold diffusion layer 6 is formed (as shown in FIG. 2b). Furthermore,
After forming the interlayer insulating film 7 on the entire surface, the diffusion layer 6
A contact hole 8 is formed by selectively opening the upper interlayer insulating film 7. Thereafter, a lead wiring 9 is formed in this contact hole 8 to manufacture a semiconductor device (as shown in FIG. 2c).
しかしながら、従来技術によれば、第１の熱酸
化膜４を通してBF2をイオン注入するため、拡散
層６中には照射損傷により結晶欠陥層５が生じ
る。そこで、この結晶欠陥層５を除去せずに層間
絶縁膜７のコンタクトホール８に取出し配線を形
成すると、結晶欠陥に起因するSiの析出が増大し
てコンタクト抵抗が大きくなり、信頼性が低下す
る。 However, according to the prior art, since BF 2 is ion-implanted through the first thermal oxide film 4, a crystal defect layer 5 is generated in the diffusion layer 6 due to radiation damage. Therefore, if the lead wiring is formed in the contact hole 8 of the interlayer insulating film 7 without removing this crystal defect layer 5, the precipitation of Si due to the crystal defect will increase, the contact resistance will increase, and the reliability will decrease. .
（発明が解決しようとする問題点）
本発明は上記事情に鑑みてなされたもので、
BF2のイオン注入により生じた拡散層中の結晶欠
陥層を除去し、コンタクト抵抗の増加を抑制しえ
る半導体装置の製造方法を提供することを目的と
する。(Problems to be solved by the invention) The present invention has been made in view of the above circumstances.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress an increase in contact resistance by removing a crystal defect layer in a diffusion layer caused by BF 2 ion implantation.
［発明の構成］
（問題点を解決するための手段と作用）
本発明は、半導体基板の表面に素子分離領域を
形成する工程と、この素子分離領域で囲まれた島
領域上に第１の熱酸化膜を形成する工程と、この
第１の熱酸化膜を通して前記島領域にBF2をイオ
ン注入する工程と、前記第１の熱酸化膜を除去す
る工程と、H2SO4とH2O2系の薬品処理を施す工
程と、HF系の薬品処理を施す工程と、前記島領
域上に第２の熱酸化膜を形成する工程とを具備
し、イオン注入時に前記島領域中に発生した結晶
欠陥層を除去することを特徴とし、コンタクト抵
抗の増加の抑制を図つたことを骨子とする。[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention includes a step of forming an element isolation region on the surface of a semiconductor substrate, and a step of forming a first isolation region on an island region surrounded by the element isolation region. a step of forming a thermal oxide film, a step of ion-implanting BF 2 into the island region through the first thermal oxide film, a step of removing the first thermal oxide film, and a step of ion-implanting BF 2 into the island region through the first thermal oxide film; and a step of removing H 2 SO 4 and H 2 . The method includes a step of applying an O2 - based chemical treatment, a step of performing an HF-based chemical treatment, and a step of forming a second thermal oxide film on the island region, so as to reduce the amount of heat generated in the island region during ion implantation. The main feature of this method is to remove the crystal defect layer caused by the contact, and to suppress the increase in contact resistance.
即ち、本発明は、第１の熱酸化膜の除去後H2
SO4、H2O2系の薬品処理を施して化学吸着酸化
することによりBF2をイオン注入時に発生した結
晶欠陥層の一部を酸化膜中に取込んだ後、HF系
薬品処理を施すことにより結晶欠陥層を軽減し、
更に第２の熱酸化膜の形成により結晶欠陥層を該
第２の熱酸化膜中に取込み欠陥層を島領域から排
除するものである。 That is, in the present invention, after removing the first thermal oxide film, H 2
A part of the crystal defect layer generated during ion implantation of BF 2 is incorporated into the oxide film by chemical adsorption oxidation using SO 4 and H 2 O 2 based chemical treatment, and then HF based chemical treatment is applied. By reducing the crystal defect layer,
Furthermore, by forming a second thermal oxide film, the crystal defect layer is incorporated into the second thermal oxide film and the defect layer is removed from the island region.
（実施例）
以下、本発明の一実施例を第１図ａ〜ｄを参照
して説明する。なお、従来と同部材は同符号を付
して説明を省略する。(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1a to 1d. Incidentally, the same members as those in the prior art are given the same reference numerals and the description thereof will be omitted.
まず、Ｎ型のシリコン基板１の表面にフイール
ド酸化膜２を形成した後、このフイールド酸化膜
２で囲まれた島領域３に第１の熱酸化膜４を形成
した。つづいて、この熱酸化膜４を通して前記島
領域３にBF2をイオン注入した（第１図ａ図示）。
次いで、前記第１の熱酸化膜４を除去した後、
H2SO4、H2O2系の薬品処理を施し、結晶欠陥層
５を化学吸着酸化して薄い酸化膜（図示せず）中
に取込む。しかる後、HF系薬品処理で上記結晶
欠陥層５の上部を除去した（第１図ｂ図示）。更
に、900℃、O2雰囲気で熱処理を行うことによ
り、前記島領域３上に厚さ200Åの第２の熱酸化
膜１１を形成するとともに、島領域３にＰ型の拡
散層６を形成した（第１図ｃ図示）。なお、この
第２の熱酸化膜１１の形成により、一部残存する
前記結晶欠陥層５は第２の熱酸化膜１１に完全に
取込まれ、拡散層６中から除外される。以下、従
来と同様、全面に層間絶縁膜７を形成した後、所
定の箇所にコンタクトホール８を形成し、更に取
出し配線９を形成して半導体装置を製造した（第
１図ｄ図示）。 First, a field oxide film 2 was formed on the surface of an N-type silicon substrate 1, and then a first thermal oxide film 4 was formed in an island region 3 surrounded by the field oxide film 2. Subsequently, BF 2 was ion-implanted into the island region 3 through this thermal oxide film 4 (as shown in FIG. 1A).
Next, after removing the first thermal oxide film 4,
A chemical treatment using H 2 SO 4 and H 2 O 2 is applied to chemically adsorb and oxidize the crystal defect layer 5 and incorporate it into a thin oxide film (not shown). Thereafter, the upper part of the crystal defect layer 5 was removed by HF-based chemical treatment (as shown in FIG. 1b). Furthermore, by performing heat treatment at 900° C. in an O 2 atmosphere, a second thermal oxide film 11 with a thickness of 200 Å was formed on the island region 3, and a P-type diffusion layer 6 was formed on the island region 3. (Illustrated in Figure 1c). By forming the second thermal oxide film 11, the partially remaining crystal defect layer 5 is completely incorporated into the second thermal oxide film 11 and excluded from the diffusion layer 6. Thereafter, as in the prior art, after forming an interlayer insulating film 7 over the entire surface, contact holes 8 were formed at predetermined locations, and lead-out wiring 9 was further formed to manufacture a semiconductor device (as shown in FIG. 1d).
本発明によれば、第１の熱酸化膜４を通して
BF2をイオン注入した後、第１の熱酸化膜４を除
去し、H2SO4とH2O2系の薬品処理を施し、更に
HF系の薬品処理を施した後、第２の熱酸化膜１
１を形成するため、上記薬品処理により結晶欠陥
層５を島領域３の表面に見掛け上移動させ、かつ
第２の熱酸化膜１１中に結晶欠陥層５を取込むこ
とができる。従つて、結晶欠陥に起因するSiの析
出が抑制され、低いコンタクト抵抗を有する拡散
層６と取出し配線９の接続が可能となる。事実、
本発明及び従来の半導体装置によるコンタクト抵
抗とコンタクトサイズ（正方形のコンタクトにお
ける一辺の長さ）との関係を調べたところ、第３
図に示す結果が得られた。同図で、イは本発明の
場合、ロは従来の場合を夫々示す。同図により、
本発明の場合が従来の場合と比べコンタクト抵抗
が約１桁低下していることが確認できる。 According to the present invention, through the first thermal oxide film 4
After ion-implanting BF 2 , the first thermal oxide film 4 is removed, H 2 SO 4 and H 2 O 2- based chemical treatment is performed, and further
After HF-based chemical treatment, the second thermal oxide film 1
1, the crystal defect layer 5 can be apparently moved to the surface of the island region 3 by the chemical treatment, and the crystal defect layer 5 can be incorporated into the second thermal oxide film 11. Therefore, the precipitation of Si due to crystal defects is suppressed, and it becomes possible to connect the diffusion layer 6 and the lead-out wiring 9 with low contact resistance. fact,
When we investigated the relationship between contact resistance and contact size (length of one side of a square contact) in the present invention and conventional semiconductor devices, we found that the third
The results shown in the figure were obtained. In the figure, A shows the case of the present invention, and B shows the conventional case. According to the same figure,
It can be confirmed that the contact resistance in the case of the present invention is reduced by about one order of magnitude compared to the conventional case.
［発明の効果］
以上詳述した如く本発明によれば、結晶欠陥層
を除去してコンタクト抵抗を低減できる半導体装
置の製造方法を提供できる。[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device that can reduce contact resistance by removing a crystal defect layer.
第１図ａ〜ｄが本発明の一実施例に係る半導体
装置の製造方法を工程順に示す断面図、第２図ａ
〜ｃは従来の半導体装置の製造方法を工程順に示
す断面図、第３図は本発明及び従来法による半導
体装置のコンタクトサイズとコンタクト抵抗との
関係を示す特性図である。
１……Ｎ型のシリコン基板、２……フイールド
酸化膜（素子分離領域）、３……島領域、４，１
１……熱酸化膜（絶縁膜）、５……結晶欠陥層、
６……拡散層、７……層間絶縁膜、８……コンタ
クトホール、９……取出し配線。
1A to 1D are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps, and FIG.
-c are cross-sectional views showing the conventional method of manufacturing a semiconductor device in order of steps, and FIG. 3 is a characteristic diagram showing the relationship between contact size and contact resistance of semiconductor devices according to the present invention and the conventional method. 1...N-type silicon substrate, 2...Field oxide film (element isolation region), 3...Island region, 4,1
1... thermal oxide film (insulating film), 5... crystal defect layer,
6...Diffusion layer, 7...Interlayer insulating film, 8...Contact hole, 9...Output wiring.
Claims (1)
工程と、この素子分離領域で囲まれた島領域上に
第１の熱酸化膜を形成する工程と、この第１の熱
酸化膜を通して前記島領域にBF2をイオン注入す
る工程と、前記第１の熱酸化膜を除去する工程
と、H2SO4とH2O2系の薬品処理を施す工程と、
HF系の薬品処理を施す工程と、前記島領域上に
第２の熱酸化膜を形成する工程とを具備し、イオ
ン注入時に前記島領域中に発生した結晶欠陥層を
除去することを特徴とする半導体装置の製造方
法。1. A step of forming an element isolation region on the surface of a semiconductor substrate, a step of forming a first thermal oxide film on an island region surrounded by the element isolation region, and a step of forming a first thermal oxide film on the island region surrounded by the element isolation region. a step of ion-implanting BF 2 into the substrate, a step of removing the first thermal oxide film, and a step of performing H 2 SO 4 and H 2 O 2- based chemical treatment;
The method is characterized by comprising a step of applying HF-based chemical treatment and a step of forming a second thermal oxide film on the island region to remove a crystal defect layer generated in the island region during ion implantation. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7112986A JPS62229934A (en) | 1986-03-31 | 1986-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7112986A JPS62229934A (en) | 1986-03-31 | 1986-03-31 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62229934A JPS62229934A (en) | 1987-10-08 |
| JPH0587016B2 true JPH0587016B2 (en) | 1993-12-15 |
Family
ID=13451653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7112986A Granted JPS62229934A (en) | 1986-03-31 | 1986-03-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62229934A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2729309B2 (en) * | 1988-12-05 | 1998-03-18 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| JP2626275B2 (en) * | 1991-02-28 | 1997-07-02 | 富士通株式会社 | Ion implantation monitoring method |
| JP2776272B2 (en) * | 1994-11-02 | 1998-07-16 | 日本電気株式会社 | Method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5238385A (en) * | 1975-09-23 | 1977-03-24 | Osamu Nakagawa | Accelerateefiring device for casttangling |
| JPS55102227A (en) * | 1979-01-29 | 1980-08-05 | Hitachi Ltd | Ion implantation |
-
1986
- 1986-03-31 JP JP7112986A patent/JPS62229934A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5238385A (en) * | 1975-09-23 | 1977-03-24 | Osamu Nakagawa | Accelerateefiring device for casttangling |
| JPS55102227A (en) * | 1979-01-29 | 1980-08-05 | Hitachi Ltd | Ion implantation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62229934A (en) | 1987-10-08 |
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