JPS62126367A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate a test by cutting an interior into sections if necessary, by providing a shift register capable of respectively performing parallel-in and parallel-out to at least one input and output lines of a logical LSI circuit to be used. CONSTITUTION:When '0' is inputted to a mode changeover line (MDSW)4 at the time of usual operation, the shift registers provided to the input and output sides of a logical LSI circuit (BLSI22, DLSI24) come to a parallel mode and the input data applied to a parallel input line TIN passes through ALSI 21-ELSI25 to send out output data to a parallel output line TDT. When '1' is inputted to MDSW4, the shift register is changed over to a serial mode and, by applying series data from a shift line SIN, required data can be set to the input/output sides of DLSI24 and DLSI22. Thereafter, by the change of the input of a clock control line CLKC5 and that of MDSW4, the operation results of ALSI21 and BLSI22 are set to the shift register in the output side and sent out as series data through a serial out-line SOT.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is an integrated circuit for logic (hereinafter referred to as logic LSI circuit), particularly for facilitating testing of internal logic circuits and connected peripheral logic circuits. For logic 1. Regarding SI circuits.

(Prior Art) Conventionally, a logic electronic circuit package is constructed by connecting a logic LSI circuit or a plurality of logic LSI circuits, and these multiplex circuit packages or a plurality of electronic circuit packages are connected. Many methods are used to configure functional devices. In such an electronic circuit package, in order to test the normality or failure diagnosis of the package, a plurality of input cover turns are applied to the input terminal of the package, and the corresponding cover turn obtained from the high-strength terminal is determined for each input cover turn. Is there a way to check if it is as expected?
ing.

(Problems to be Solved by the Invention) However, as the number of logic LSI circuits constituting an electronic circuit package increases, or as the internal logic circuit of the logic LSI 1j becomes larger, the electronic circuit package If a large number of input buttons are not applied for the test, it will be possible to not only judge the failure but also identify the location of the failure (fault logic LSI circuit). It has the problem that it is necessary.

The purpose of the present invention is to eliminate the above-mentioned problems and use
At least one input/output line of the II LSI circuit should be provided with a shift register capable of parallel in/parallel out, and if necessary, the inside of the electronic circuit package can be separated to transfer data (test button). The objective is to provide an 8I circuit for logic that can be accessed and removed to facilitate testing.

(Means for Solving the Problems) The invention provides a logic LSI circuit having a plurality of input lines and a sand-covered output line.
and parallel input between the internal logic circuit and the output line.
A shift register capable of parallel output is provided, and a shift-out line provided on the input line side and a shift-in line provided on the output line 1 are connected. It also has a mode switch that simultaneously switches the modes of these two sets of shift registers, and further includes a clock signal line that is input to these two sets of shift registers, and a clock control line that simultaneously controls this clock signal. be done.

Normally, this logic LSI circuit is connected to other logic LSI circuits.
, are connected in columns to form an electronic circuit package.1 In normal logic operation, the input given to the parallel in terminal of the shift register of this logic LSI circuit is directly output from the parallel out terminal. , these shift registers do not participate in logical operations. However, when a mode switching signal is applied to this logic LSI circuit, the input applied to the parallel-in terminal is cut off, and data is input serially from the shift-in line of the shift register provided on the input side, and the data is input to the output side. Data can be set in the shift register and the shift register on the input side. After that, depending on the arithmetic clock of this electronic/child circuit package, the clock to the shift register is temporarily stopped by the clock control line, and the logic L is output based on the set input data.
8I is operated, the output from the previous stage of the LSI for this logic is taken into the shift register provided on the input side, and the calculation result of the LSI for this logic is taken into the shift register on the output line side, and then the output is input again. By switching to shift mode, the contents of these shift registers can be increased to the outside as serial data from the shift-out line on the output line side. Also, by setting the parallel input cover turn of the electronic circuit package and obtaining the parallel output cover turn at this time, it is possible to simultaneously obtain the results of the internal calculations of this logic LSI and the side peripheral logic LSIs. Divided electronic circuit packages can be tested simultaneously without providing a large number of intermediate terminals and with a small number of test patterns.

(Example) Hereinafter, an example of the xylophone i% will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In a logic LSI circuit having a plurality of input lines and a plurality of output lines, an input line 1 and an output line 1 are connected in parallel and in parallel, respectively. This shows a case where a shift register that can be output is provided.

In the figure, the input m (11+1 is a shift register with parallel in/parallel out (hereinafter referred to as ASI), G
)1 are provided, and parallel input lines AA, AB...AM
Parallel output corresponding to this input device, @! AQA.

AQB...AQM, shift-in line SIN and money owner,
The output line AQA also serves as shift alarm 1-aiAsO'l"i. The parallel output line also serves as the internal logic circuit (hereinafter LS
IA) 2, l, 5IA2 output edge output line 1
It is connected to parallel inputs iHA, BB, .

Also, parallel output of H2BO3? fMBQA, HQH・
・BQN is provided corresponding to the parallel input machine, shift in, IJBIN is ASI, and shift out #A of G1
It is disconnected from SOT, and the shift out line so'r also serves as the output line BQA. -10,000 mode switching line (hereinafter referred to as MD)
SW) 4 is connected to the mode switching input line of As)l, Gl and BSRG3, and the clock line (hereinafter referred to as CLK) is connected to the same (ASRGI) via GA.
has been entered. A negative input is connected to the clock control i (hereinafter referred to as CI, KC) to another input terminal of the gate GA.If a logic value "0" is given to Ml) SW 4 in the above m configurations, @ ASRGI and B 81 (,
G3 is set to parallel mode by the selection gate (SEL) each has inside, and each input is given to the D-type flip 70 tube connected to each selection gate 5ELK, and the rising edge of the clock always given to CI, 6. All inputs are held, and all held signals are output at the falling edge of the clock. l CLK5 is always a fM! i+(i is”
0'' and @1'' is input only when stopping the clock. Therefore, when MDSW4 is 0'', FiLSIA2 receives parallel input from the previous stage, performs a logical operation, and sends parallel output to all subsequent stages.

Next, when the logical value @1” is given to MDSW4, A
Both SL(G1↓ and BS⇠G3 are set to serial mode with the above selection gate 8ELK, their respective parallel input lines are cut off, and the serial in line SI
The input from N is first input to D of AelGl according to the clock.
Transferred to type 7 lip-flop, serial out, serial in dB of BSRG3 from 1% A30T
The data is sent to the SIN, then sequentially transferred to the D-type lip flop of HIO2, and then sent to the serial output SOT.

FIG. 2 shows a block diagram of an embodiment in which an electronic circuit package is constructed using a conventional logic LSI circuit in addition to the logic LSI circuit shown in FIG. The fifth logic LSI circuit (hereinafter referred to as AL81 and L
ILSI, CLSI, L) LSI construction BLSI) 2
1, 22, 23, 24 and 25 are connected in series, and the parallel output of one logic LSI circuit serves as the parallel input for the next stage.

The parallel input T I N of this electronic circuit package is connected to ALSI21, and the parallel output TOT of this electronic circuit package is connected from ELδ125. In addition, HL8I22, Di, and 5I24 are configured with logic LSI circuits of the present invention, and are connected to the shift-out lines 1ED1 and 5I24 of the BLSI22, and are connected to the shift-out lines 1ED1 and 5I24 of the BLSI22, and are connected to the shift-out lines 1ED1 and 5I24 of the BLSI22.
Each of the 24 shift-out lines serves as a shift-in [8IN Shift Arrangement] Iwao SOT of the electronic circuit package. Furthermore, each mode switching line MDSW4 and clock control line C of HL, 5I22 and DL8124
The clocks I and KC5 to CLK6 are connected in a line and connected to the external connection terminal of the electronic 1gj path package.

In the above configuration, electronic circuit package? When connected to a functional device and performing all operations, the MD SW 4 is always given a logic value of "0", and as explained in the WJ1 diagram, the human output g111 of each of the BLSI 22, DL, and 8124 is provided. The assigned shift register is in parallel mode, and the manual data ViALS given to T' I N is input without participating in logic @ calculation.
I 21 , BLSI 22 , El, Sl 2
The output data is sent to the TOT via the logic circuit No. 5.

- 10,000, when the logical value "1" is given to MDSW4, BL
The shift registers provided on the input/output side of each of SI 22 and DLSI 24 are switched to serial mode, and by providing serial data from SIN in synchronization with the clock, the output side of DL8I24 and the input 9111,
Furthermore, by setting arbitrary data to the output of BL8122 (till and the shift register at the input end. Then, when the required data is set), CLKC
By setting the logic value of 5 to 15 and stopping the supply of clock to the shift register, the set data of the shift register described above can be held as is.Next, if necessary, set arbitrary data to TIN and set the data of MDSW4. Change the logical value to 10', set the logical value of CLKC5 to t"o", and immediately after one clock, change the logical value of MD8W4 to "
When changed to lo, Al of the input data given to TIN
.

The calculation result by 5I21 is sent to Hl, the input terminal 1 shift register of 5I22, and the human power 4JA of BLSI22
B for manual data held in II shift register
The result of the operation by the LSI 22 is set in the shift register of this output 1111, and the result of the operation of the input data is similarly set in the next shift register, and this result data is further sent out as serial data via the SOT. . Note that only the output data of the ELSI 25 is outputted in parallel from the TOT at once.

Therefore, by adopting this circuit configuration, predetermined test data can be set in the input terminal of the electronic circuit package, the manual rule of the logic LSI circuit of the present invention, and the shift register of the output ill, and the calculation results of each logic circuit can be set. It can be done manually by performing all the movements.

In the embodiment shown in FIG. 2, conventional logic LSI circuits and non-inventive logic LSI circuits are alternately connected, but all non-inventive logic LSI circuits may be placed in any position as required. However, there is no restriction on everyone.

(Effects of the Invention) As described above in detail, by rearranging the logic LSI 1g1 circuit arrangement of the present invention in the logic circuit package,
If the input terminal of an electronic circuit package is not only an output terminal, but also a small number of additional input/output edges and control lines, a large number of intermediate terminals are provided in the logic operation circuit, and the electronic circuit package can be divided. A similar test can be carried out if the test is carried out separately, and this has the effect of significantly simplifying the test of a single electronic circuit package.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment 4/11 of the invention, and FIG. 2 is a block diagram of an embodiment of an electronic circuit package including a logic LSI 1pJ path of the invention. 1.3... Parallel-in/parallel-out shift register (As) LG, BSR (j), 2
,21゜23.25...Logic LSI circuit (L, 81
A,AI,,9I. CLS I, ELS I), 4...Mode switching line (MD8'W), 5...Clock control line (CI, K
C), 6...clock/line (CLK), 22.24...
・Logic LSI circuit of the present invention (BLSl, Dl, SI)
. 7. \Representative Patent Attorney
Susumu Hara Diagram 2

Claims (1)

[Claims] In a logic LSI circuit having a plurality of input lines and a plurality of output lines, a parallel input line provided between the input line and the internal logic circuit and between the internal logic circuit and the output line, respectively. Two sets of shift registers capable of parallel output, a mode switching line that simultaneously switches the mode of these two sets of shift registers, a clock control line that simultaneously controls the clock signals input to these two sets of shift registers, and an input line. A logic integrated circuit comprising a connection line connecting a shift-out line of the shift register provided on the side and a shift-in line of the shift register provided on the output line side.