JPS62125652A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPS62125652A
JPS62125652A JP60265652A JP26565285A JPS62125652A JP S62125652 A JPS62125652 A JP S62125652A JP 60265652 A JP60265652 A JP 60265652A JP 26565285 A JP26565285 A JP 26565285A JP S62125652 A JPS62125652 A JP S62125652A
Authority
JP
Japan
Prior art keywords
cap
base
ceramic
recess
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60265652A
Other languages
Japanese (ja)
Inventor
Shigeharu Yamamura
山村　重治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60265652A priority Critical patent/JPS62125652A/en
Publication of JPS62125652A publication Critical patent/JPS62125652A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1616—Cavity shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent a ceramic cap from displacing to a ceramic base by forming a projection for preventing the cap from displacing to the base by engaging the cap with a recess of the base. CONSTITUTION:A thicker projection 8 than a periphery 4 is formed at the center of a cap 3 for closing a hole of a recess 9 of a base 1. The width of the projection 8 coincides with the recess 9 of the ceramic base 1, the projection 8 is engaged with the recess 9 in case of baking in oxidative atmosphere, the periphery 4 of the cap 3 is seated on a solder glass 5, and the projection 8 is engaged with the recess 9 to position the cap 3 to the base 1. Accordingly, when fusion-bonding with the solder glass, the base 1 and the cap 3 are positioned by engaging the projection 8 with the recess 9. Thus, it is not affected by the influences of a vibration at conveying time, gas-flow at baking time, and the cap 3 can be accurately fusion-bonded to the base 1. Thus, the operating efficiency in case of handling is improved to improve a yield.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高密度実装に最適なリードレスチップキャリア
集積回路パッケージの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a leadless chip carrier integrated circuit package that is optimal for high-density packaging.

〔従来の技術〕[Conventional technology]

従来、この種のパッケージ構造を第３図と第４図により
説明する。Conventionally, this type of package structure will be explained with reference to FIGS. 3 and 4.

セラミックベース１は配線用メタライズ電極２を含む多
層セラミックで構成されており、このセラミックベース
１に、Ａｕ−８ｉ共晶はんだ、Ａｇ系エポキシ接着剤な
どによりシリコンチップ６をマウントシ、シリコンチッ
プ上の配線領域の一部（図示省略、一般にポンディング
パッド部と呼ばれる）と、セラミックベース１の配線用
メタライズ電極２の一部とをＭ線又はＭ線７を用いて接
続し、さらに、酸化性雰囲気中で焼成する。このベース
１をセラミックキャップ３にて施蓋し、接合部にソルダ
ーガラス５を溶着することによってシールしていた。The ceramic base 1 is composed of a multilayer ceramic including metallized electrodes 2 for wiring, and a silicon chip 6 is mounted on the ceramic base 1 using Au-8i eutectic solder, Ag-based epoxy adhesive, etc., and the wiring on the silicon chip is mounted. A part of the area (not shown, generally called a bonding pad part) and a part of the wiring metallized electrode 2 of the ceramic base 1 are connected using an M wire or an M wire 7, and further, in an oxidizing atmosphere. Fire it with This base 1 was covered with a ceramic cap 3 and sealed by welding solder glass 5 to the joint.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のセラミック型リードレスチップキャリア
集積回路パッケージは、セラミックベース上面が平坦と
なっているので、セラミックベースと、セラミックキャ
ップをシール用のソルダーガラスで溶着する際、溶着機
のベルトコンベアーの振動、酸化性雰囲気ガス流などの
影響により、セラミックキャップがずれて溶着されると
いう欠点を有し、その後の集積回路選別工程、スフＩＪ
　−ニング工程などで、ハンドリングの際マガジンラツ
クに引っかかるなど作業性の低下、及びＩＣソケットを
用いる工程において、セラミックキャップがずれている
為、ＩＣソケットに挿錨できず、選別、スクリーングが
不可能となり歩留りの低下を来たすなどの欠点がある。The above-mentioned conventional ceramic leadless chip carrier integrated circuit package has a flat top surface of the ceramic base, so when the ceramic base and ceramic cap are welded with the solder glass for sealing, vibrations of the belt conveyor of the welding machine are generated. , due to the influence of oxidizing atmosphere gas flow, etc., the ceramic cap has the disadvantage that it is welded in a misaligned manner, and the subsequent integrated circuit selection process, SFP IJ
-During the processing process, work efficiency is reduced as the product gets caught in the magazine rack during handling, and in the process of using an IC socket, the ceramic cap is misaligned, making it impossible to anchor the IC socket, making sorting and screening impossible. This has drawbacks such as a decrease in yield.

本発明はセラミックベースに対するセラミックギャップ
の位置ずれを防止する集積回路パッケージを提供するも
のである。The present invention provides an integrated circuit package that prevents misalignment of the ceramic gap relative to the ceramic base.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は凹陥７小にチップをマウントしたベースと、そ
の凹陥部の開口を施蓋するキャップとをソルダーガラス
にて気密に４Ｎ止してなる集積回路パッケージにおいて
、前記キャップに、ベースの凹陥部に嵌合して該ベース
に対する位置ずれを防止する突起部を設けたことを特徴
とする集積回路パッケージ。The present invention provides an integrated circuit package in which a base with a chip mounted in a recess (7) and a cap that closes the opening of the recess are hermetically sealed at 4N with solder glass. 1. An integrated circuit package, comprising a protrusion that fits into the base to prevent displacement with respect to the base.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を示すリードレスチップキャ
リア集積回路パッケージの斜視図であり、第２図は第１
図の断面図である。FIG. 1 is a perspective view of a leadless chip carrier integrated circuit package showing one embodiment of the present invention, and FIG.
FIG.

セラミックベース１は配線用メタライズ電極２を含む多
層セラミックで構成され、その凹陥部９の上縁にはシー
ル用のソルダーガラス５が焼付けられている。このセラ
ミックベース１に、Ａｕ−８ｌ共品はんだ、Ａｇ系エポ
キシ接着剤などにより（図示省略）、シリコンチップ６
をマウントし、シリコンチップ６上の配線領域の−Ｆ’
ｉ１Ｓ　（図示省略、一般にポンディングパッド部と呼
ばれる０とセラミックベース１の配線用メタライズド電
極２の一部とをＡｕ線又はＭ線７を用いて接続した構成
は従来と同じである。The ceramic base 1 is composed of a multilayer ceramic including a metallized electrode 2 for wiring, and a solder glass 5 for sealing is baked on the upper edge of the recessed part 9. A silicon chip 6 is attached to this ceramic base 1 using Au-8L solder, Ag-based epoxy adhesive, etc. (not shown).
-F' of the wiring area on the silicon chip 6.
i1S (not shown; the configuration in which 0, generally called a bonding pad section, and a part of the interconnect metallized electrode 2 of the ceramic base 1 are connected using an Au wire or an M wire 7 is the same as the conventional one).

本発明はベース１の凹陥部９の開口を閉塞するキャップ
３の中火部に周囲部４より肉厚を０．１〜１．０ｍｍの
範囲で厚くした突起部８を設けたものである。In the present invention, a protrusion 8 is provided on the medium heat portion of the cap 3 that closes the opening of the concave portion 9 of the base 1, the protrusion 8 being thicker than the surrounding portion 4 by 0.1 to 1.0 mm.

その突起部８０幅はセラミックベース１の凹陥部９に合
致する寸法を有する。酸化性雰囲気中で焼成する際には
、キャップ３の突起部８をセラミックベース１の凹陥部
９に吠合し、キャラ１３０周囲部４をソルダーガラス５
０表面に着座させるとともに、突起部８と凹陥部９との
嵌合によりベース１に対するキャップ３の位置決めをす
る。この状態で通常の方法によりソルダーガラス５を溶
融してセラミックベース１とセラミックキャップ３とを
溶着することによりシールを行う。The width of the protrusion 80 has a dimension that matches the recess 9 of the ceramic base 1. When firing in an oxidizing atmosphere, the protruding part 8 of the cap 3 is fitted into the recessed part 9 of the ceramic base 1, and the surrounding part 4 of the character 130 is attached to the solder glass 5.
0 surface, and the cap 3 is positioned relative to the base 1 by fitting the protrusion 8 and the recess 9. In this state, sealing is performed by melting the solder glass 5 and welding the ceramic base 1 and the ceramic cap 3 together using a conventional method.

したがって、ソルダーガラスで溶着する際に、ベース１
とキャップ３とは、突起部８と凹陥部９との嵌合により
位置決めされるから、搬送時の振動、焼成時のガス流な
どの影響を受けることがなく、キャップ３はベース１に
正確に溶着する。Therefore, when welding with solder glass, base 1
Since the cap 3 and the cap 3 are positioned by fitting the protrusion 8 and the recess 9, the cap 3 is not affected by vibrations during transportation or gas flow during firing, and the cap 3 is accurately positioned on the base 1. Weld.

なお、上記実施例において、セラミック型ＩＪ　−ドレ
スチップキャリア集積回路パッケージについて説明した
が、ガラスシール法の他の集積回路パッケージ、例えば
セラミック型ビングリッドアレーパッケージなどに適用
できることは勿論である。In the above embodiments, a ceramic type IJ-dressed chip carrier integrated circuit package has been described, but it goes without saying that the present invention can be applied to other integrated circuit packages using the glass seal method, such as a ceramic type bin grid array package.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はガラスシール法によるセラ
ミック型集積回路パッケージのセラミックキャップの肉
厚を周囲部よりその中央部を厚くし凸形状の突起部を設
け、その突起部をセラミックベースの凹陥部に挿入し、
ソルダーガラスで溶着することにより、セラミックキャ
ップがセラミックベースに位置ずれせずに溶着すること
ができ、これにより、ハンドリングの際の作業性の向上
、ＩＣソケットを用いる選別、スクリーニング工程など
で歩留りの向−七を図れる効果がある。As explained above, the present invention makes the thickness of the ceramic cap of the ceramic integrated circuit package using the glass sealing method thicker in the center than in the surrounding area, and provides a convex protrusion, and the protrusion is connected to the concave part of the ceramic base. Insert it into
By welding with solder glass, the ceramic cap can be welded to the ceramic base without shifting its position, which improves workability during handling and improves yield in sorting and screening processes using IC sockets. -It has the effect of achieving 7.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す斜視図、第２図は第１
図の断面図、第３図は従来の集積回路パッケージの斜視
図、第４図は第３図の断面図である。 ■・・・セラミックベース、２・・・配線用メタライズ
ド電極、３・・・セラミックキャップ、４・・・セラミ
ックキャップの周囲部、５・・・シール用のソルダーガ
ラス、６・・・シリコンチップ、７・・・ん線又はＭ線
、８・・セラミックキャップの突起部、９・・セラミッ
クベースの凹陥部 第２図FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG. 2 is a perspective view showing one embodiment of the present invention.
3 is a perspective view of a conventional integrated circuit package, and FIG. 4 is a sectional view of FIG. 3. ■... Ceramic base, 2... Metallized electrode for wiring, 3... Ceramic cap, 4... Surroundings of ceramic cap, 5... Solder glass for sealing, 6... Silicon chip, 7...N wire or M wire, 8...Protrusion of ceramic cap, 9...Concave part of ceramic base Fig. 2

Claims (1)

【特許請求の範囲】[Claims] （１）凹陥部にチップをマウントしたベースと、その凹
陥部の開口を施蓋するキャップとをソルダーガラスにて
気密に封止してなる集積回路パッケージにおいて、前記
キャップに、ベースの凹陥部に嵌合して該ベースに対す
る位置ずれを防止する突起部を設けたことを特徴とする
集積回路パッケージ。(1) In an integrated circuit package in which a base with a chip mounted in a recessed part and a cap that covers an opening in the recessed part are hermetically sealed with solder glass, the cap has a chip mounted in the recessed part of the base. An integrated circuit package characterized in that it is provided with a protrusion that fits and prevents displacement with respect to the base.
JP60265652A 1985-11-26 1985-11-26 Integrated circuit package Pending JPS62125652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60265652A JPS62125652A (en) 1985-11-26 1985-11-26 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60265652A JPS62125652A (en) 1985-11-26 1985-11-26 Integrated circuit package

Publications (1)

Publication Number Publication Date
JPS62125652A true JPS62125652A (en) 1987-06-06

Family

ID=17420109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60265652A Pending JPS62125652A (en) 1985-11-26 1985-11-26 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPS62125652A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016069265A (en) * 2014-09-29 2016-05-09 日本碍子株式会社 Joint method for joining ceramic-made package member constituting housing to ceramic-made lid member

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016069265A (en) * 2014-09-29 2016-05-09 日本碍子株式会社 Joint method for joining ceramic-made package member constituting housing to ceramic-made lid member

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