JPS6211831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention A/D converts a composite video input signal at a first sampling frequency, and converts the A/D converted data to a second sampling frequency approximately equal to the first sampling frequency. This relates to a device that performs D/A conversion at a sampling frequency to obtain a composite video output signal.
It is an object of the present invention to output a composite video signal that does not cause deterioration on the receiving screen when the composite video output signal is received by a television receiver.

FIG. 1 is a diagram for explaining a conventional example.

Conventionally, when synchronizing an input composite video signal with an external signal, a frame synchronizer 1 shown in FIG.
was used. This frame synchronizer 1 samples the input composite video signal with a clock synchronized with the color subcarrier, performs A/D conversion, and converts the A/D converted data into one field using a clock (write clock) synchronized with the color subcarrier. The data is written to a memory with a capacity of 100 kHz, and read from the memory using a read clock synchronized with external signals (vertical drive signal VD, horizontal drive signal HD, color subcarrier SC) that are asynchronous with the input composite video signal.

In this frame synchronizer 1, when overtaking or overtaking occurs in the memory due to the difference in frequency between the read clock and the write clock, that is, when the memory read timing is faster than the write timing, the overtaking or being overtaken occurs. Detects the point in time, corrects the data in the memory that is already stored one field before so that it becomes the data of the current field, and then performs D/A conversion, which is almost equal to the input composite video signal synchronized with the external signal. This is a device that obtains video signals. In this way, the frame synchronizer 1 uses the correlation between the fields of the video signal to obtain a video signal with little deterioration from the input video signal synchronized with an external signal, so it always requires a memory of one field or more. It is. Therefore, there was a drawback that the size of the device was large and the cost was high.

The present invention eliminates the above-mentioned conventional drawbacks. One embodiment will be described below with reference to the accompanying drawings.

2 to 6 relate to the configuration of the present invention, and FIG. 2 is a block diagram of the synchronization device of the present invention;
3 to 5 are circuit diagrams of the input N-point control circuit 4, vertical synchronization signal detection circuit 7, and phase detector 8 in the block diagram of FIG. 2, respectively, and FIG. 6 explains the operation of the present invention. FIG. The case where the composite video input signal is a color signal will be explained below.

In Fig. 2, 2 is a sampling signal generation circuit that generates a sampling signal A (SPA) of the first sampling frequency (N times the frequency of the color subcarrier of the input composite video signal), and 3 is a sampling signal generator that clamps the input composite video signal. , is an A/D converter that samples the clamped signal using the sampling signal A (SPA) and converts it into an 8-bit digital signal. It is set so that

4 is an input N-point control circuit, which allows the sampling signal A (SPA) to pass through when there is no trigger pulse (TP1) from the timing control circuit 10 (described later), and passes the sampling signal A (SPA) when there is a trigger pulse (TP1). The strobe signal A (STA) is output by inhibiting N consecutive pulses.

Reference numeral 5 denotes an output N-point control circuit, which has a second sampling frequency approximately equal to the first sampling frequency, and which outputs a sampling signal B given from the outside.
(SPB), timing control circuit 1 described later
When there is no trigger pulse (TP2) from 0, the sampling signal B is passed through, and when there is a trigger pulse (TP2), the sampling signal B is passed through.
It operates to output a strobe signal B (STB) in which N consecutive pulses of (SPB) are inhibited. 6 stores the output of the A/D converter 3 using a strobe signal A (STA), reads out the stored contents using a strobe signal B (STB), and stores Q outputs of the A/D converter 3. It is a first-in, first-out memory (hereinafter referred to as FiFo memory) that can perform

Reference numeral 7 denotes a vertical synchronization signal detection circuit, which utilizes the fact that the state in which all bits are logic "0" at the output of the A/D converter 3 continues continuously for a longer time in the vertical synchronization signal period than in the horizontal synchronization signal period. to detect the vertical synchronization signal. 8 is a phase detector and strobe signal A
The value S of the up-down counter circuit 24 (described later in FIG. 5), which counts up by one by (STA) and counts down by one by strobe signal B (STB), and the set values Q ₁ and Q ₂ (Q ₁ <Q ₂ < S), and the results are used as comparison signals CP1 and CP2.
Output as . 9 is a D/A converter that reads out FiFo memory 6 using strobe signal B (STB).
Converts the digital output of the converter into an analog signal. 1
0 is a timing control circuit that controls the timing of each of the circuits 2 to 9 described above.

FIG. 3 is a circuit diagram showing details of the input N-point control circuit 4, in which 11-1 to 11-(N+1) are JK flip-flops, and 12 is an AND circuit. Due to the trigger pulse TP1 from the timing control circuit 10, the output terminal Q of the J-K flip-flop 11-1 becomes logic "1", and this output outputs the sampling signal in the J-K flip-flops 11-2 to 11-(N+1). Shifted by A (SPA). When J-K flip-flop 11-(N+1) becomes logic "1", J-K flip-flop 1
1-1 is cleared and becomes logic “0”, and again,
Output of flip-flop 11-1 (logic “0”)
are J-K flip-flops 11-2 to 11-(N
+1), and all JK flip-flops 11-1 to 11-(N+1) become logic "0". At this time, the sampling signal A is output from the output terminal of the JK flip-flop 11-2.
(SPA), the gate signal GT1 which becomes logic "0" is obtained, and by ANDing this signal and the sampling signal A in the AND circuit 12, a strobe that inhibits the sampling signal A for N times is obtained. Signal A (STA) is obtained.

Similarly, in FIG. 3, sampling signal A (SPA) is applied to sampling signal B (SPB) provided from the outside, gate signal GT1 is applied to gate signal GT2, strobe signal A is applied to strobe signal B, and trigger pulse TP1 is applied to externally applied sampling signal B (SPB). By replacing each with the trigger pulse TP2, the timing control circuit 10 generates a gate signal GT2 which becomes logic "0" for N periods of the sampling signal B if the trigger pulse TP2 is present, and this signal GT2 and the sampling signal B By performing the AND operation, an output N-point control circuit 5 that outputs strobe signals B (STB) obtained by inhibiting N sampling signals B can be realized.

FIG. 4 is a circuit diagram showing details of the vertical synchronization signal detection circuit 7, in which 13 is an inverter and 14 is an 8-bit AND circuit. 15 is a counter circuit which uses the sampling signal A (SPA) as a clock and counts when the clear terminal CL is logic "1";
If the count value is greater than or equal to the value M described later, a carry signal is sent.
CR becomes logic “1”. 16 is the above carry signal
The output of A/D converter 3, which is the output terminal of CR, is
By clamping the input composite video signal, all bits are set to logic "0" during the synchronization signal period, so the output of the AND circuit 14 becomes logic "1" during the synchronization signal period, and the counter circuit 15 outputs the sampling signal. Count A (SPA).

Outside the synchronization signal period, at least one of the output bits of the A/D converter 3 has a logic "1", so the output of the AND circuit 14 becomes a logic "0", and the counter circuit 15 is cleared. Ru. The value M of the counter circuit 15 when the carry signal CR is generated is set so that no carry occurs in the counter circuit 15 during the horizontal synchronizing signal period, and a carry occurs at least once during the vertical synchronizing signal period. Ru.

FIG. 5 is a circuit diagram of the phase detector 8. 1 in the diagram
7-20 are J-K flip-flops, 21-22
is a 2-input AND circuit, 23 is a 2-input OR circuit, and 24 is an n-bit up/down counter circuit. The up/down switching of this counter circuit is performed when the input to the U/D terminal is at a high level. state, it is down state when it is low level. 25
are the value S of the up-down counter circuit 24 and the set value
In the comparator circuit A that compares _Q1 , the comparison output CP1 becomes logic "1" when S< _Q1 . 26 is the value S of the up-down counter circuit 24 and the set value Q ₂ (Q ₁
In comparison circuit B that compares <Q ₂ ), when S>Q ₂
CP2 becomes logic "1". When Q ₁ < S < Q ₂ ,
Comparison outputs CP1 and CP2 are both logic "0". 27 is a clock generation circuit, the first or second
The clock signals P1 have a frequency ( ₀ = 1/T'> ₂ ) slightly higher than the sampling frequency ( ₁ 〓 ₂ ≒ 1/T), have a duty of 25%, and are out of phase with each other by T'/4. -P4 and negative clock signals *P1 to *P4, which are inverted clock signals, are generated.

In Fig. 5, strobe signal A (STA)
The JK flip-flop 17 becomes logic "1" due to this pulse, and its output is latched in the JK flip-flop 18 at the falling edge of the clock signal *P1. When the Q output terminal of JK flip-flop 18 becomes logic "1", JK flip-flop 17 is cleared. JK flip-flop 18 is cleared by clock signal *P3. Therefore, the output terminal Q of the JK flip-flop 18, which is set to logic "1" by the falling edge of the strobe signal A, is output from the falling edge of the clock signal *P1 to the falling edge of *P3.
The logic becomes "1" during the period of T'. The Q output terminal of the JK flip-flop 18 is input to an AND circuit 21 and a U/D terminal for setting the counting up/down mode of the up/down counter circuit 24.
When the output terminal Q of the J-K flip-flop 18 is logic "1", the up-down counter circuit 24 is set to the count-up mode, and the clock signal P2 is input to the clock terminal CK through the AND circuit 21 and the OR circuit 23, Only one count will be added. Similarly, strobe signal B (STB)
When there is a pulse of J-K flip-flop 19
is set, which causes clock signal P4 to become
The up-down counter circuit 24 and the AND circuit 2
2. It is input through the OR circuit 23, but the u/D
Since the terminal is at low level, only one count is counted down.

Comparison circuit A 25 and comparison circuit B 26 output the value S and set value of up-down counter circuit 24, respectively.
Compare Q ₁ and Q ₂ and convert up/down counter circuit 2
If the value S of 4 is smaller than the value _Q1 , the comparison output CP1 is set to logic "1", and if the value S is larger than the value _Q2 , the comparison output CP2 is set to logic "1". When the value S is between the value _Q1 and the value _Q2 , the comparison outputs CP1 and CP2 are both logic "0".

FIG. 6 is a timing chart for explaining the operation of the block diagram of FIG. 2, in which a indicates the signal waveforms before and after the vertical synchronization signal of the input composite video signal including an equalization pulse. b is a carry signal CR of the vertical synchronization signal detection circuit 7, and the value M is a carry signal CR of the vertical synchronization signal period.
is reset, and the carry pulse E1~ as shown in the figure
Assume that the setting is such that E6 is output.
c and d are comparison circuit A25 and comparison circuit B2, respectively.
6 comparison outputs CP1 and CP2 signal waveforms, section A
When , comparison output CP1 is logic “1”, comparison output CP
2 is logic “0”, and comparison output CP except section A
1 and CP2 are both logic "0". e is the signal waveform of the trigger pulse TP2 from the timing control circuit 10, and e is the waveform of the gate signal GT2 of the output N-point control circuit 5.

The operation shown in FIG. 2 will be explained in detail below based on the timing chart shown in FIG.

The input composite video signal is input to a sampling signal generation circuit 2 and an A/D converter 3, and the sampling signal generation circuit 2 synchronizes with the color subcarrier and outputs a frequency N times that of the color subcarrier (first sampling frequency).
A sampling signal A (SPA) is generated.

The A/D converter 3 clamps the input video signal, samples it using the sampling signal A (SPA), and performs A/D conversion. This A/D conversion output is written into the FiFo memory 6 by the strobe signal A (SPA) from the input N-point control circuit 4. Strobe signal A (STA) is sent to phase detector 8
It is also input to the up-down counter circuit 24, and the value S of the up-down counter circuit 24 is counted up by one. FiFo memory 6
The contents are read out by strobe signal B (STB) and D/A converted by D/A converter 9. Strobe signal B (STB) is sent to phase detector 8
The value S of the up-down counter circuit 24 is counted down by one.

The value S of the up-down counter circuit 24 of the phase detector 8 at this time is approximately equal to the number of outputs of the A/D converter 3 stored in the FiFo memory 6. The comparison output between this value S and set values Q ₁ and Q ₂ is the comparison output CP.
1 and output to the timing control circuit 10 as CP2. When the timing control circuit 10 receives a carry signal CR (carry pulses E1 to E6) indicating a vertical synchronization signal period as shown in FIG. Read the comparison outputs CP1 and CP2 of 8.

If the comparison output CP1 is logic "1", it indicates that the number of data stored in the FiFo memory 6 is small, that is, the frequency of the sampling signal B is higher than the sampling signal A, and the timing control circuit 10 outputs the N point. A trigger pulse TP2 is output to the control circuit 5, and N is applied to the sampling signal B.
Inhibit is applied for N points, and reading of data from the FiFo memory 6 is stopped for N points. During this time,
The data output from FiFo memory 6 before being inhibited (because of the vertical synchronization signal period, FiFo memory 6
The output of the memory 6 (all bits are logic "0") is subjected to D/A conversion.

Therefore, when the trigger pulse TP2 is output, the number of samples to be D/A converted by the sampling signal B, which corresponds to the vertical synchronization signal, is increased by N times from the number of samples to be A/D converted by the sampling signal A. However, the period of the restored vertical synchronization signal is longer by N sampling signal B periods than when the trigger pulse TP2 is not output.

In this way, the lack of data caused by the second sampling frequency being higher than the first sampling frequency can be solved by converting the number of samples that are D/A converted during the vertical synchronization signal period into A/D conversion during the vertical synchronization signal period. This is absorbed by increasing the number of samplings.

Next, if the comparison output CP2 is logic “1”,
Since the number of data stored in the FiFo memory 6 is large, that is, the frequency of the sampling signal A is higher than the sampling signal B, the timing control circuit 10 sends the trigger pulse TP1 to the input N-point control circuit 4. output, inhibit the sampling signal A by N times,
Stop writing to the FiFo memory 6 for N pieces.
During this time, the A/D converter 3 also receives the sampling signal A.
Since A/D conversion is performed continuously based on the above, N outputs of the A/D converter 3 are equal to the N sampling signals A inhibited.
This means that it is not written to FiFo memory 6 and is discarded.

Therefore, the number of samples that are D/A converted using the sampling signal B as a vertical synchronizing signal when the trigger pulse TP1 is output is N fewer than the number of samples that are A/D converted using the sampling signal A. That is, the trigger pulse TP
The period of the vertical synchronizing signal restored when 1 is output is shorter by N points of the sampling signal B.
In this way, excess input data that occurs when the first sampling frequency is higher than the second sampling frequency is absorbed by discarding the A/D conversion output of the vertical synchronization signal.

When comparison outputs CP1 and CP2 are both logic "0", the timing control circuit 10 does not output a trigger pulse, and the sampling signal A of the input vertical synchronization signal
The sampled and A/D converted data is input to the FiFo memory 6 as it is, and is also taken out from the FiFo memory 6 and subjected to D/A conversion.

For example, in the case of Fig. 6, the carry signal CR shown in b
When the pulse E1 is, the comparison outputs CP1 and CP2 are respectively logic "0" as shown in c and d, so the timing control circuit 10 causes the output N-point control circuit 5 to trigger as shown in FIG. 6e. Pulse TP2
Output. This trigger pulse TP2 generates a gate signal GT2 as shown in FIG.
Since only writing is performed without reading data from the FiFo memory 6, the number of data stored in the FiFo memory 6, that is, the up-down counter circuit 24
The value S becomes larger than the value _Q1 , and the comparison output CP1 becomes logic "0" as shown in FIG. 6c. The timing control circuit 10 receives the carry pulse E in FIG. 6b.
2 to E6, the values of comparison outputs CP1 and CP2 are also read, but since both are logic "0",
Trigger pulses TP1 and TP2 are not output. In this way, the timing control circuit 10 controls the reading and writing of the FiFo memory 6 during the vertical synchronization signal period so that the number of data stored in the FiFo memory 6 is between the value _Q1 and the value _Q2 . It's summery.

As described above, in the present invention, the sampling signal A
The number of samples to be D/A converted by the sampling signal B during the vertical synchronization signal period can be reduced by N points, or
As a result, the period of the vertical synchronization signal of the reproduced composite video signal becomes longer or shorter for the N points of sampling signal B, but it is completely absorbed by sampling signal B given from the outside. A composite video signal synchronized with can be obtained.

As explained above, in the present invention, a composite video input signal is A/D converted using a sampling signal A having a first sampling frequency, and the A/D converted data is converted into a second signal having a second sampling frequency that is approximately equal to the first sampling frequency.
When performing D/A conversion using sampling signal B with a sampling frequency of It is absorbed by using water. Then,
When the data is A/D converted and omitted, the period of the vertical synchronization signal reproduced by D/A conversion is shorter than when the data is not omitted. Similarly, when A/D converted data is used in duplicate, the period of the reproduced vertical synchronization signal becomes longer than in the case where it is used in duplicate.

Although the period of the vertical synchronization signal reproduced in this manner becomes longer or shorter, the vertical positional shift of the scanning line of the television receiver due to this is slight and does not pose a problem.

Also, when the period of the vertical synchronizing signal becomes longer or shorter, it means that the period of some of the horizontal signals becomes shorter or longer, but the horizontal signal of the television receiver of
Since the AFC pull-in time is fast, there is no effect on the screen. Also, when the input signal is a color signal,
The sampling frequency is selected to be N times the frequency of the color subcarrier, but at this time, the amount by which the vertical synchronization signal period becomes longer or shorter is because the sampling signal B given from the outside is processed in units of N pieces. The subcarrier continuity and interlace conditions are satisfied, the reproduced color subcarrier is completely synchronized with the external signal (sampling signal B), and the beat between the sampling signal B and the reproduced color subcarrier does not occur. do not have. As described above, the present invention provides a synchronization device that can reproduce a composite video signal in which the color subcarrier is completely synchronized with the external signal (sampling signal B) and the reproduced image does not deteriorate, using a small amount of memory and a simple memory. This can be achieved using a control circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronization device using a conventional frame synchronizer, FIG. 2 is a block diagram of a synchronization device that implements a video signal synchronization method according to an embodiment of the present invention, and FIG. 4 is a specific circuit diagram of the vertical synchronizing signal detection circuit 7 of FIG. 2, FIG. 5 is a specific circuit diagram of the phase detector 8 of FIG. 2, and FIG. The figure is a timing chart for explaining the operation of the synchronization method of the present invention. 2...Sampling signal generation circuit, 3...A/
D converter, 4... Input N-point control circuit, 5... Output N-point control circuit, 6... FiFo memory, 7... Vertical synchronization signal detection circuit, 8... Phase detector, 9...
D/A converter, 10...timing control circuit, 1
1-1 to 11-(N+1)...J-K flip-flop, 12...AND circuit, 13...Inverter, 14...AND circuit, 15...Counter circuit, 16...Carry signal output terminal, 17 ~20
...J-K flip-flop, 21-20 ... AND circuit, 23 ... OR circuit, 24 ... Up-down counter circuit, 25 ... Comparison circuit A, 26 ...
...Comparison circuit B, 27...Clock generation circuit.

Claims (1)

[Claims] 1. A/D converting a composite video input signal at a first sampling frequency, and subjecting the A/D converted and temporarily stored data to a second sampling frequency approximately equal to the first sampling frequency. In a device that obtains a composite video output signal by performing D/A conversion at a frequency, the vertical synchronization signal period is changed for each vertical synchronization signal period depending on the excess or deficiency of input/output data due to the difference between the first and second sampling frequencies. A video signal synchronization method characterized in that at least part of the data is deleted or at least part of the data in the vertical synchronization signal period is used redundantly. 2. By counting the difference in the number of sampling pulses caused by the frequency difference between the first sampling frequency and the second sampling frequency, and reading this counted value P during the vertical synchronization signal period, the counted value P is set to the set value _P1 . If it is smaller, by redundantly using a part of the A/D converted data during the vertical synchronization signal period, D/A conversion is performed _one extra time, and the value obtained by adding S ₁ to the count value P is set as a new P. The value of
If the count value P is larger than the set value P ₂ (P ₂ > P ₁ ), the data converted from A/D during the vertical synchronization signal period is
If the value obtained by deleting ₂ S and performing D/A conversion and subtracting S ₂ from the count value P is the new value of P, and if the count value P is between the set values P ₁ and P ₂ , then A/
2. The video signal synchronization method according to claim 1, wherein an operation beyond directly performing D/A conversion on D-converted data is performed every vertical synchronization signal period. 3. The input composite video signal is a color signal, and the first
Claim 2, characterized in that when the sampling frequency of is selected to be N (N: an integer) times the input color subcarrier frequency, the values of S ₁ and S ₂ are set to be a natural number multiple of N. The described video signal synchronization method.