JPS62114264A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the software error of a bit line mode by burying a higher impurity density first conductivity type first semiconductor buried region than the impurity density of the first conductivity type semiconductor substrate in the substrate and the first conductivity type semiconductor layer disposed on the substrate to contact with the second conductivity type fist semiconductor region connected with a bit line. CONSTITUTION:Since a P<+> type diffused region 16 is contacted with an N<+> type drain region 7 as a bit line region, the extension of the region 7 is decided by the impurity density of the region 16. The density of the region 16 is increased as long as P-N junction resistance is allowed to reduce the width of a depletion layer of the region 7. Most of electrons generated due to the incident radiation such as alpha-ray are collected to the region 7 by funneling effect. Since the funneling length is proportional to the width of the depletion layer, it can be largely improved against the software error of a bit line mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that can reduce soft errors in memory cell mode.

[Prior Art] FIG. 3 is a sectional view showing the structure of a semiconductor memory device disclosed in, for example, Japanese Patent Publication No. 60-4595. In addition,
This figure has been slightly modified to facilitate the detailed description of the invention below. First, the configuration of this device will be explained. In the figure, an n+ type drain region 7, an n+ type source region 8. N1 type diffusion regions 3 are formed at intervals from each other, and p" type diffusion regions t16 having an impurity concentration higher than the impurity concentration of the p type silicon substrate 1 are formed as n+ type diffusion regions 3.n1 type source A region 8.
It is embedded in the p-type silicon substrate 1 so as to be in contact with the p-type silicon substrate 1.

2 is a silicon oxide film for element isolation. Further, a gate insulation m9 is formed on the p-type silicon substrate 1 between the n+ type drain fl[t47 and the 0+ type source region 8, and this gate insulation! ! A gate electrode 10 is formed on 9 . Further, a capacitor insulating film 4 is formed on the n1 type diffusion region 3, and a capacitor insulating film 4. A capacitor N pole 5 is formed on the silicon oxide film 2 for element isolation. n
+ type diffusion region 3 and capacitor insulation! #4 and the main 1 abacitor electrode 5 constitute a memory cell which is an information storage capacitor, and information is stored by accumulating charge in the n+ type diffusion region 3 of the storage node which is to become one electrode of this capacitor. . The p-type silicon substrate 1, the n+-type drain 1a1, the n+-type source region 8, the gate insulating film 9, and the gate electrode 10 constitute a transfer gate transistor, and this gate voltage +mio is connected to a word line for selecting a memory hill. has been done. Further, an oxide film 11 is formed so as to cover the capacitor electrode 5° and the gate electrode +io:yi+, and a bit line 13 for selecting a memory cell is formed on this oxide film 11. A contact hole 12 is provided in the oxide film 11, and the n+ type drain region 7 and the bit line 13 are connected through this hole.

Next, the operation of this device will be explained. The state in which electrons are accumulated in the 01 type diffusion region 3, which serves as the charge accumulation region of the memory cell, is expressed as IQ.
1'' Do. The potential of the n" type drain order 1I117 as a bit line region is a high potential in advance, and in many cases, the potential is a high potential.
It is held at voltage VcC.

Here, the potential of the word line rises and the potential of the gate transistor 1"D[+10 of the transformer 77 rises.
When the voltage becomes higher than the voltage, the transfer gate transistor is turned on, and the n+ type drain region 70+ type source region 8 and the gate 4 type diffusion region 3 become conductive. Therefore, if the stored information of the memory cell is "l Q IT", that is, electrons are accumulated in the n+ type diffusion region 3, the potential of the n+ type drain region 7 decreases due to the conduction of the transformer 77 gate transistor, and Memory information is “1 pa,
In other words, when no electrons are accumulated in the n'' type diffusion region 3, the potential of the n+ type drain region 7 does not change to the B potential.Then, these changes in bit line potential are sensed. An amplifier (not shown) senses and reads stored information from the memory cell.

[Problem to be Solved by the Invention 1] In a memory cell in a conventional semiconductor memory device, the charge storage region is formed in the n-shaded region in the p-type silicon substrate 1, so that radiation such as α-rays can be absorbed into the memory chip. Of the electrons and holes that are generated by entering the , the electrons accumulate charge! T! !
There is a problem in that the information is collected in the n1 type diffusion region 3, inverting the original stored information and causing a malfunction (hereinafter referred to as a soft error). In order to eliminate such drawbacks, in the conventional example shown in FIG. 3, an n+ type diffusion region 6 having an impurity concentration higher than that of the p-type silicon substrate 1 is formed around the n+ type diffusion region 3. By adding a p-n junction capacitance, the memory cell capacity is increased, and at the same time, the extension of the depletion layer between the n+ type diffusion region 8 and the p-type silicon substrate 1 is suppressed. This reduces the amount of charge collected in the n+-type diffusion region 3 and improves soft errors.

On the other hand, soft errors are memory cycle time dependent, as shown by the solid line in Figure 5, and are inversely proportional to the memory cycle time. It is expressed as the sum of the bit line mode soft errors that occur in the bit line region, which increases as a result. memory cell n”
The n-type diffusion region 6 formed under the shape diffusion region 3 is very effective in improving soft errors in the memory cell mode as described above, but it is very effective in improving soft errors in the pin 1-line mode. Improvement is required. A soft error in the bit line mode occurs when the transistor turns on, information is read from the memory cell to the n + 10-shaped rain region 7 as the bit region, the sense amplifier operation starts, and the latch is determined. This is caused by the incidence of alpha rays during the period.

As a method for improving soft errors in the bit line mode, there is a conventional example disclosed in Japanese Patent Application Laid-open No. 127291/1983 as shown in FIG. In this conventional example, an n-type silicon substrate 14 is used instead of the p-type silicon substrate 1 in FIG. 3, a p-type epitaxial cell layer 15 is formed on this substrate, and the n-type silicon substrate 14 and the p-type epitaxial layer By applying a reverse voltage between 15 and 15, electrons generated by α rays, noise, etc.
Also, the n+ type drain region 7 serving as the bit line region is prevented from reaching the n+ type drain region 7. However, Document C, Hu”Qrif
t Co11ection of Alpha G
eneratedCarriers and Qes
ign Implication”, l 5S
CC' 82 Technical Dig
est, PP, 18-19.1982, the charge collected for the incidence of α rays is mostly F
This is due to the tunneling effect.
ing length is proportional to the depletion layer width. In the conventional example shown in Figure 4,
It is thought that the reverse bias at the p0 junction is effective in preventing electrons generated by the incidence of α particles from reaching the memory cell and bit line region through diffusion, but the above-mentioned l"LInneltnQ effect It is useless against.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can reduce bit line mode soft errors.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a first semiconductor buried region of a first conductivity type having a higher impurity concentration than an impurity concentration of a semiconductor substrate of a first conductivity type, in a bit line. It is embedded in a semiconductor substrate and a semiconductor layer of a first conductivity type on this substrate so as to be in contact with a first semiconductor region of a second conductivity type to be connected.

[Function] In the present invention, the semiconductor substrate is embedded in the semiconductor substrate of the first conductivity type and the semiconductor layer of the first conductivity type thereon so as to be in contact with the first semiconductor region M of the second conductivity type, which is the bit wA5A area. The first semiconductor buried region of the first conductivity type has an impurity L'lJ 9 degree higher than the impurity degree m of the semiconductor substrate.
The extension of the depletion layer in region ii is suppressed, thereby reducing the number of electrons generated by the incidence of radiation that are collected in the first semiconductor region, thereby reducing bit line mode soft errors.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

Note that in the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 shows a semiconductor layer (I!8) which is an embodiment of the present invention.
FIG. The configuration of this example is 7A
The differences from the configuration in Figure 3 are as follows.

That is, a p-type epitaxial layer 15 is formed on a p-type silicon substrate 1, and this p-type epitaxial layer 1
5 on which an n+ type drain region 7 and an n+ type drain region 8 are formed.
．． N+ type diffusion regions 3 are formed at intervals from each other. Further, the p-type epitaxial layer 15. It is embedded in a p-type silicon long plate 1. n of p+ type diffusion region 16
The impurity concentration of the portion in contact with the +-type drain region 7 is preferably one order of magnitude higher than the impurity concentration of the p-type long silicon plate 1.
It is preferable that it is 017 to 1020 circles/C118. Also, p
The +-shaped swelling area 6 has been removed.

In this way, since the p" expansion 11!li region 16 is in contact with the 0+ type drain region 7 serving as a bit line region, the extension of the depletion layer of this n1 type drain region 7 is the impurity of the p" expansion diffusion region 16. Determined by concentration. By setting the concentration of the p4 type diffusion a region 16 to be as high as the pn1a breakdown voltage allows, the width of the depletion layer of the 11' type drain region 7 becomes smaller than in the cases of FIGS. 3 and 4. As mentioned above, most of the electrons generated by incident radiation such as alpha rays are F.
N+ type drain region 7 due to Ullneling effect
Since the length of the Funnc I ino is proportional to the width of the depletion layer, the embodiment of the present invention is different from the first conventional example.
This has a significant improvement effect on bit/line mode soft errors, which were not considered in the figure.

In addition, in the embodiment shown in FIG. 1, p as shown in FIG.
The + type diffusion 111[16 may be buried in the p type epitaxial layer 15 so as to be in contact with the n + diffusion IIwi3 as a memory cell storage node, thereby also reducing soft errors in the memory cell mode.

Further, as shown in FIG. 2 as an example of the present invention, a p-type epitaxial layer 1 is formed so that the p+-type expansion region 16 is in contact with an n+-type drain region 7 serving as a bit line region.
5. Not only is it buried in the p-type silicon long plate 1, but also the impurity concentration is higher than the impurity concentration in the p-type silicon long plate 1.
+ type diffusion region 17 as a memory cell storage node
A p-type epitaxial layer 15.1 is in contact with the type 1 diffusion region 3 and the n+ type source region 8 of the transfer gate transistor. It may also be embedded in the p-type silicon long plate 1. The n+ type expansion area 3 of this p+ type expansion area '17. n
The impurity concentration of the portion in contact with the p-type source region 8 is preferably one order of magnitude higher than the impurity concentration of the p-type long silicon plate 1.
It is good if it is 7-1020 pieces/Cl113. In this case, not only soft errors in the bit line mode but also soft errors in the memory cell mode can be reduced.

In addition, a p+ type expansion w4 having an impurity concentration higher than the impurity concentration of the p type long silicon plate 1 is provided so as to be in contact with the n'' expansion diffusion 1id (not shown) as an internal node of the sense amplifier connected to the bit line 13. The p-type epitaxial layer 15.1) may be buried in the long silicon plate 1.The impurity concentration of the portion in contact with the internal node of this p+ type expanded region is preferably p-type. 1017 to 102'pieces/'CII, which is one order of magnitude higher than the impurity level of silicon long plate 1
I) is preferable.

As a result, soft errors at internal nodes of the sense amplifier can be reduced, and countermeasures against pit line mode soft errors in semiconductor memory devices are greatly improved.

[Effects of the Invention] As described above, according to the present invention, the first semiconductor substrate of the first conductivity type has an impurity concentration higher than the impurity concentration of the first conductivity type semiconductor substrate.
Since the semiconductor buried brass region is embedded in the semiconductor substrate and the semiconductor layer of the first conductivity type thereon so as to be in contact with the first semiconductor region of the second conductivity type connected to the pit line, the pit line mode is suppressed. A semiconductor memory device that can reduce soft errors can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a sectional view showing the structure of a semiconductor memory device according to another embodiment of the invention. FIG. 3 shows the structure of a conventional semiconductor memory device! It is a li side view. FIG. 4 is a sectional view showing the structure of another conventional semiconductor memory device. FIG. 5 is a diagram showing the relationship between soft errors in memory cell mode and human line mode and memory cycle time in a semiconductor memory device. In the figure, 1 is a p-type silicon substrate, 2 is a silicon oxide film for element isolation, 3 is an I)+ diffusion region, 4 is a capacitor insulating film, 5 is a gabacitor electrode, 7 is an n" type train region, and 8 is an n+ a shaped source region, 9 a gate insulating film, 10 a gate electrode, 11 an oxide film, 12 a contact opening, 1
3 is a bit line, 15 is a p-type epitaxial layer, 16.1
7 is a p+ type diffusion region. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Otori 1
Figure 2 Figure 17: P+W41 diffusion area Figure 3 Figure 4

Claims (7)

[Claims] (1) a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on the semiconductor substrate; and a second semiconductor layer formed on the semiconductor layer and connected to a bit line.
a first semiconductor region of a conductivity type; and a second semiconductor of a second conductivity type, which is formed on the semiconductor layer at a distance from the first semiconductor region, and includes a charge storage region for storing information in a part thereof. a first conductivity type semiconductor memory device that is embedded in the semiconductor layer and the semiconductor substrate so as to be in contact with the first semiconductor region, and has an impurity concentration higher than that of the semiconductor substrate; A semiconductor memory device comprising a region. (2) The semiconductor memory device according to claim 1, wherein the semiconductor layer is an epitaxially grown layer. (3) The impurity concentration of the first semiconductor buried region in contact with the first semiconductor region is 10^1^7 to 10^2^0 particles/cm, which is one order of magnitude higher than the impurity concentration of the semiconductor substrate.
The semiconductor memory device according to claim 1 or 2, which is ^3. (4) Further, a second semiconductor layer of the first conductivity type is embedded in the semiconductor layer and the semiconductor substrate so as to be in contact with the second semiconductor region, and has an impurity concentration higher than that of the semiconductor substrate.
A semiconductor memory device according to any one of claims 1 to 3, comprising a semiconductor buried region. (5) The impurity concentration of the second semiconductor buried region in contact with the second semiconductor region is 10^1^7 to 10^2^0 particles/cm, which is one order of magnitude higher than the impurity concentration of the semiconductor substrate.
The semiconductor memory device according to claim 4, which is ^3. (6) Furthermore, a second node, which is formed on the semiconductor layer and is connected to the bit line, is an internal node of the sense amplifier.
a third semiconductor region of a conductive type; a first semiconductor region embedded in the semiconductor layer and the semiconductor substrate so as to be in contact with the third semiconductor region, and having an impurity concentration higher than that of the semiconductor substrate;
6. The semiconductor memory device according to claim 1, further comprising a conductive type third semiconductor buried region. (7) The impurity concentration of the third semiconductor buried region in contact with the third conductor region is 10^1^7 to 10^2^0 pieces/cm^, which is one order of magnitude higher than the impurity concentration of the semiconductor substrate.
6. The semiconductor memory device according to claim 6, which is No. 3.