JPS61239660A - Semiconductor memory circuit device - Google Patents

Abstract

PURPOSE:To increase storage capacitance, to improve a soft-error resistance by alpha-rays and to reduce an occupying area by forming a groove at a node in a memory cell and forming a layer having a conduction type reverse to a substrate to the side surface of the groove and base thereof in a resistance load type SRAM. CONSTITUTION:A groove 104 is shaped from a window 103 in a gate oxide film 102 on a P-type Si substrate 101, and coated with P-added poly Si 105, 106. An N<+> diffusion layer 107 is formed from poly Si 105, and As ions are implanted to shape N<+> layers 108, 109. An opening 111 is bored to an inter-layer insulating film 110, and poly Si 112 having high resistance connected to the poly Si 105 is formed. An Al electrode 115 is connected to the N<+> layer 109 through an opening 114 in an inter-layer insulating film 113. Elements are isolated by a field oxide film 116 and a P-type channel stopper 117. In a memory cell according to the constitution, the quantity of charges stored by a P-N junction on the side surface of the groove is increased, and a soft-error resistance by alpha-rays is improved while an occupying area can be reduced without minimizing the capacitance area of the cell.

Description

[Detailed description of the invention] □ 1 c″5′″0″1ll)[:]11
The present invention relates to a semiconductor memory circuit device, and more particularly to a semiconductor memory circuit device with increased resistance to soft errors caused by 1K alpha rays.

[Conventional technology]

In recent years, resistive load type static random access memory IJ using insulated gate field effect transistors has been developed.
As for (SRAM), the degree of integration has been improved, the memory cells have been reduced, and power consumption has been reduced.

[Problem that the invention seeks to solve]

In the conventional resistive load type SRAM mentioned above, the current flowing through the memory cell is reduced in order to reduce power consumption, and the capacitance attached to the nodes of the transistors that make up the memory cell is reduced due to the size of the memory cell. This resulted in inconveniences such as soft errors caused by alpha rays.

This will be explained using FIG. 3. FIG. 3 shows a configuration diagram of a memory cell of a resistive load type SRAM. Here, the capacitance of node A is composed of the drain diffusion layer capacitance of transistor Q1, the source/drain diffusion layer capacitance of transistor Q3, and the gate capacitance of 1.2 transistor Q2, and the capacitance of node B is also similar to node A. By the way, the area of memory cells has been reduced due to higher integration, so the capacitance at nodes A and B of the memory cells has decreased. As a result, the accumulated charges at nodes A and B decreased, resulting in the disadvantage that they were susceptible to soft errors caused by alpha rays. Furthermore, in order to reduce power consumption, resistors R1 and R2 have higher resistance values than conventional ones to reduce the current flowing through the memory cells. However, because a high resistance is used, it takes longer than conventional methods for the potentials at nodes A and H of the memory cell, which fluctuate during writing and reading, to reach a steady value of a high level value or a low level value. It became so.

This has the disadvantage that it is susceptible to soft errors caused by alpha rays.

[Failure to solve the problem]

A semiconductor memory circuit device of the present invention includes an insulated gate field effect transistor and a load resistor formed on a conductivity type semiconductor substrate.
A groove is formed in a predetermined region of the semiconductor substrate, an impurity diffusion layer of opposite conductivity type is formed on the side and bottom surfaces of the groove, and an impurity of opposite conductivity is contained inside the groove in contact with the side and bottom surfaces of the groove. Polycrystalline silicon is formed, and the polycrystalline silicon and the load resistor are electrically connected.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

This embodiment relates to a resistive load type static random access memory using MOS transistors. Figure 1 is Figure 2A for explaining this embodiment.
A sectional view of the memory cell taken along the line -A', and FIG. 2 is a plan view of the memory cell.

In FIG. 1, a trench 104 is formed in a window 103 of a gate oxide film 102 on a P-type silicon substrate 101. As shown in FIG. Polycrystalline silicon 105,10 with phosphorus added thereon
6 is formed, the N+ type impurity diffusion layer 107 is formed by phosphorus diffusion from the polycrystalline silicon 105 doped with phosphorus, and the N+ type impurity diffusion layers 108 and 109 are formed by arsenic ion implantation. polycrystalline silicon 105
A high-resistance polycrystalline silicon 112 is connected to the first interlayer insulating film 110 through an opening 111. The aluminum electrode 115 is connected to the N medium impurity diffusion layer 109 through the opening 114 of the second interlayer insulating film 113. Field oxide M116 and P-type channel stopper 117 are for isolating the elements.

Next, in the plan view of the memory cell shown in FIG. 2, grooves 104 are formed at the pair of left and right nodes, and on the side and bottom surfaces of the grooves 104, N-type impurity diffusion layers 108 of the source and drain are formed. There is a type impurity diffusion layer 107, and these N0 type impurity diffusion layers completely form a PN junction with the P type silicon substrate. Note that the high-resistance polycrystalline silicon 112 and aluminum electrode 115 are omitted in FIG.

In a memory cell having such a structure, the digit line is an aluminum electrode 115, the word line is a polycrystalline silicon electrode 106,
The load resistor is made of high-resistance polycrystalline silicon 112, and the gate of the driver transistor is made of polycrystalline silicon 105 to constitute a memory circuit, and information is written and read.

〔Effect of the invention〕

As explained above, the present invention provides a resistive load type static random access memory in which a groove is provided at the node of a memory cell, and an impurity diffusion layer of a conductivity type opposite to that of the substrate is provided on the side and bottom surfaces of the groove. There is. In a memory cell configured in this way, even when the load resistance is increased to reduce the current flowing through the polycrystalline silicon in order to reduce power consumption, the impurity diffusion layer provided on the side surface of the trench Yo! 1
Since the 11PN junction is formed and the capacitance increases, the amount of accumulated charge increases and the resistance to soft errors caused by α rays improves. Furthermore, even if the planar area of the memory cell is made smaller, the capacitance area can be compensated for by making the groove deeper.

Therefore, by reducing the capacitance area of the memory cell, the planar area of the memory cell can be reduced, improving the degree of integration and reliability of the semiconductor memory circuit device.

can be increased.

[Brief explanation of the drawing]

6-FIG. 1 shows A of a semiconductor memory circuit device according to an embodiment of the present invention.
-A' line sectional view, FIG. 2 is a plan view thereof, and FIG. 3 is a configuration diagram of a resistive load type memory cell. ]01...PW silicon substrate, 102...
...gate oxide film, 103...window of gate oxide film, 104...groove, 105, 106...
・Polycrystalline silicon, 107,108°109...
・N0 type impurity (171J diffusion layer, 110, 113...
...Interlayer insulating film, 11.1, 114...Opening, 112...High resistance polycrystalline silicon, 115
. . . Aluminum electrode, 116 . . . Field oxide film, 117 . . . P-type channel stopper. 17=Kaya 20) 3 times

Claims (1)

[Claims] In a semiconductor memory circuit device in which an insulated gate field effect transistor and a load resistor are formed on a semiconductor substrate of one conductivity type, a groove is formed in a predetermined region of the semiconductor substrate, and impurities of an opposite conductivity type are formed on the side and bottom surfaces of the groove. A diffusion layer is formed, polycrystalline silicon containing impurities of an opposite conductivity type is formed inside the groove and in contact with the side and bottom surfaces of the groove, and the polycrystalline silicon and the load resistor are electrically connected. A semiconductor memory circuit device characterized in that: