JPH0828428B2 - Static type semiconductor memory - Google Patents

Description

The present invention relates to a static semiconductor memory.

[Conventional technology]

FIG. 3 shows an example of the structure of a static semiconductor memory cell, which includes two load resistors 24 and 25 and four MOS transistors.
FIG. 4 is a partial cross-sectional view of a conventional static type semiconductor memory cell formed on a P-type substrate 44 according to the circuit of FIG.

In FIG. 3, load resistors 24 and 25 are drive MOSs, respectively.
The load of the transistors 20 and 21 supplies the charge from the power supply line 28 to the charge storage nodes 26 and 27 to drive the drive MOS transistors 20 and 2.
Reference numeral 1 represents a flip-flop circuit that is connected between the charge storage nodes 26 and 27 and the ground line 29 to form a flip-flop circuit.
The S-transistors 22 and 23 are turned on by receiving the signal from the word line 30 at their gates, and writing of data in the data lines 31 and 32 or reading of data in the cells to the data lines 31 and 32 is performed.

FIG. 4 shows a cross section of one of the two information transfer MOS transistors 40, the drive MOS transistor gate 41 and the load resistor 42 connected to the information transfer MOS transistor 40,
P-type substrate 44, drive MOS transistor gate 41, load resistance 4
Insulating films 45 and 56 are interposed between the two to insulate them. . Transfer MOS transistor gate 43 and drive M
Each of the OS transistor gates 41 is formed by doping the first polycrystalline silicon layer with a high concentration of impurities, and the load resistor 42 is formed by doping the second polycrystalline silicon layer with a low concentration of impurities. However, only the end region on the side opposite to the connection end with the drive MOS transistor gate 41 is used as the power supply wiring portion 47 by increasing the concentration of the doped impurities to increase the conductivity. The resistance cover 48 protects the portion of the load resistor 42 other than the power supply wiring portion 47 from doping when the power supply wiring portion 47 is doped with a high concentration of impurities.

[Problems to be solved by the invention]

In the conventional static type semiconductor memory described above, both ends of the load resistor doped in the memory cell having a low concentration are power supply wiring portions in which one is highly doped with impurities, and the other is the same drive MOS transistor. Since it is in contact with the gate, the subsequent heat treatment causes impurities to diffuse into the low impurity concentration region from the high concentration region through the contact surface, so that a resistance length sufficient to maintain the resistance value is required. In the 64K level, the one using a resistance length of 6 μm or more is the mainstream, so
In the future, even if the degree of integration is further increased, the resistance length cannot be shortened, and the load resistance length determines the length of the memory cell.

[Means for solving problems]

A static semiconductor memory according to the present invention is a static semiconductor memory in which charges are stored in a charge storage node via a load resistance, and a low resistance gate wiring formed as a gate of a driving transistor and the gate wiring are provided. A first insulating film formed so as to cover the first insulating film, and the first insulating film having one end directly connected to the gate wiring via a first connection hole selectively formed in the first insulating film. A first load resistor formed on the film, and a second insulating film formed so as to cover the first load resistor,
One end is directly connected to the other end of the first load resistor via a second connection hole selectively formed in the second insulating film and is formed via the second insulating film, and the like. The end is the first
And a second load resistor formed on the upper part of the connection hole, wherein the first load resistor is entirely formed of a high resistance layer.

Therefore, the resistance length can be set to a sufficient length irrespective of the size of the memory cell, and there is no problem even if impurities are diffused from the other high concentration impurity regions into the low impurity region of the load resistance through the contact surface, and High-density integration is possible.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. The circuit example shown in FIG. 3 is also applied to this embodiment.

FIG. 1 is a partial sectional view of a memory cell included in an embodiment of a static semiconductor memory of the present invention.

One information transfer MOS transistor 3 in this embodiment
The drive MOS transistor gate 1 and the load resistor 2 connected to the drive MOS transistor gate 1 and the load resistance 2 are both formed on the P-type substrate 13 in the same configuration as that of the conventional memory cell shown in FIG. The transistor gate 1 and the gate 4 of the information transfer MOS transistor 3 are heavily doped, and the load resistor 2 is made of lightly doped polycrystalline silicon, and an insulating film 7 is interposed therebetween. Further, a further load resistor 5 is formed of the same lightly doped polycrystalline silicon on the load resistor 2 via a similar insulating film 8 and is connected to the drive MOS transistor gate 1 of the load resistor 2. The end opposite to the connection end is in contact with the extension of the load resistor 5 filled in the contact hole 10 formed in the insulating film 8. The end of the load resistor 5 is similarly
It is connected to the power supply aluminum wiring 12 formed in the contact hole 11 formed in the insulating film 9 covering the load resistor 5.

With the above-described structure, the present embodiment allows the load resistance length to be sufficiently long even if impurities diffuse from the drive MOS transistor gate 1 in the high impurity concentration region through the contact surface, and the size of the memory cell is reduced. The degree of integration can be increased without being restricted by the load resistance length.

FIG. 2 is a partial cross-sectional view of a memory cell included in another embodiment of the static semiconductor memory of the present invention.

In the structure of this embodiment, instead of the insulating film 9 and the power source aluminum wiring 12 of the previous embodiment shown in FIG. 1, a resistance cover 14 for protecting the load resistance 5 is covered except for the terminal region, and the high voltage is applied to the terminal region. The impurity is doped at a high concentration to enhance the conductivity and be used as the power supply wiring section 15. Therefore,
Even when impurities are diffused from the drive MOS transistor 1 and the high-concentration impurity regions of the terminal region into the load resistors 2 and 5, the load resistance length can be made sufficiently long and the degree of integration can be increased as compared with the previous embodiment. It is the same.

Although the two layers of the load resistors 2 and 5 are used in both of the embodiments, the resistance length can be increased regardless of the memory cell area by increasing the load resistance in the same manner as 3 or 4. Also, the resistance length can be suppressed to a constant value to increase the integration degree.

Further, it is easily understood that the load resistance configuration described in this embodiment can be applied to circuit configurations other than the circuit shown in FIG.

〔The invention's effect〕

INDUSTRIAL APPLICABILITY As described above, the present invention has a load resistor made of polycrystalline silicon having a multilayer structure with an insulating film interposed therebetween, and the respective resistance layers are sequentially connected in series through the connection holes formed in the insulating film. By contacting and connecting with, the resistance length can be made sufficiently long even if impurities diffuse into the low impurity concentration region of the load resistance from the high concentration region through the contact surface,
Further, since the resistance length does not determine the size of the memory cell, there is an effect that high density integration can be achieved.

[Brief description of drawings]

FIG. 1 is a partial sectional view of a memory cell included in one embodiment of a static semiconductor memory of the present invention, FIG. 2 is a partial sectional view of a memory cell included in another embodiment, and FIG. 3 is a static semiconductor. 6-element memory cell circuit diagram of the memory,
FIG. 4 is a partial sectional view of a conventional example of a static semiconductor memory cell. 1 ... Drive MOS transistor gate, 2,5 ... Load resistance,
3 ... Information transfer MOS transistor, 4 ... Gate of information transfer MOS transistor, 6,7,8,9 ... Insulation film, 10,11 ... Contact hole, 12 ... Power supply aluminum wiring, 13 ...
P-type substrate, 14 ... Resistor cover, 15 ... Power supply wiring part, 20, 2
1 …… Drive MOS transistor, 22,23 …… Information transfer MOS transistor, 24,25 …… Load resistance, 26,27 …… Charge storage node, 28 …… Power supply line, 29 …… Grounding wire, 30 …… Word line,
31,32 …… Data line.

Claims (1)

[Claims] 1. A static type semiconductor memory in which charges are accumulated in a charge accumulation node via a load resistor, and a low resistance gate wiring formed as a gate of a driving transistor is covered with the gate wiring. Formed on the formed first insulating film and the first insulating film whose one end is directly connected to the gate wiring through a first connection hole selectively formed in the first insulating film Through the first load resistance, the second insulating film formed so as to cover the first load resistance, and the second connection hole selectively formed in the second insulating film. A second end having one end directly connected to the other end of the first load resistor and formed through the second insulating film and the other end formed above the first connection hole.
Static load semiconductor memory, wherein the first load resistor is entirely formed of a high resistance layer.