JPH0321103B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to highly integrated semiconductor devices, and in particular to semiconductor devices formed such that a part of the information storage capacity overlaps above a switching transistor. It is related to storage devices.

[Background of the invention]

A conventionally known one-transistor type MOS random access memory has a MOS transistor for switching, as shown in a plan view in Fig. 3 and a cross-sectional view in the Y direction (for one bit of memory cell) in Fig. 4. 1 and a capacitor 2 for storing information is selected by a word line (Al line) 3 and a data line (diffusion layer) 4.
In FIGS. 3 and 4, 5 is a substrate, 6 is an insulating film for isolation between elements, 7 is a gate oxide film, 8 and 12 are first layer polycrystalline silicon, 9 is an interlayer insulation film, and 4 and 10 are diffusion films. 11 is an inversion layer, and 22 is a contact hole.

As can be seen from the figure, since the capacitor 2 for storing information is two-dimensionally arranged on the same plane as the switching transistor 1 so as not to overlap with each other, the cell area of the memory cell increases.

[Purpose of the invention]

An object of the present invention is to analyze the above-mentioned conventional problems and provide a semiconductor device with an extremely small required area.

[Structure of the invention]

The present invention reduces the memory cell area by providing at least a portion of the storage capacitor so as to overlap above the switching transistor,
This makes it possible to improve the degree of integration of MOS memory.

That is, the present invention provides a plurality of word lines, a plurality of data lines provided to intersect with the word lines,
In a semiconductor device having a plurality of memory cells provided at the intersections of the word line and the data line, the memory cell has a capacitor for storing information and a switching transistor for controlling reading and writing of information to the capacitor. The switching transistor includes a gate insulating film, a gate electrode, a source region, and a drain region, and the capacitor includes a first conductive film and a first conductive film provided on the first conductive film. and a second conductive film provided on the capacitive insulating film, the capacitive insulating film is a multilayer insulating film, and the first conductive film is provided on an element isolation insulating film. the first conductive film is electrically connected to one of the source region and the drain region, and the data line is The source region and the drain region are electrically connected to the other region of the source region and the drain region, and two adjacent memory cells among the plurality of memory cells have the source region and the drain region electrically connected to the data line. the other of the regions is shared, the gate electrode of the switching transistor is electrically connected to the word line, and the data line has an interlayer insulating film on the second conductive film. A semiconductor device characterized in that a plurality of word lines, a plurality of data lines provided to intersect with the word lines, and a plurality of word lines and data lines are provided. In a semiconductor device having a plurality of memory cells provided at intersections with a The switching transistor has a gate insulating film, a gate electrode, a source region, and a drain region, and the capacitor includes a first conductive film, a capacitive insulating film provided on the first conductive film, a second conductive film provided on the capacitive insulating film, the first conductive film extending from above the element isolation insulating film so that an end thereof is located on the gate electrode; The first conductive film is electrically connected to one of the source and drain regions, and the data line is electrically connected to the other of the source and drain regions. , two adjacent memory cells among the plurality of memory cells share the other of the source region and the drain region electrically connected to the data line, and a gate electrode of the switching transistor; are electrically connected to the word line, and the first conductive film has substantially vertical sidewalls facing each other when viewed in cross section, and the height of the sidewall is equal to the height of the sidewall. A semiconductor device characterized in that the thickness of the first conductive film is higher than that of the first conductive film.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIGS. 1 and 2 show a plan view and a cross-sectional view of an example of a semiconductor memory device according to the present invention (for 2-bit memory cells). As can be seen from the figure, in the present invention, the specific resistance is 15Ω・cm, and the crystal axis direction is <100Ω.
＞ A 1.5 μm thick element isolation oxide film 6 and an 800 Å thick gate SiO ₂ are formed on a part of the P-type silicon substrate 5.
Membrane 7, film thickness 500 Å, first polysilicon gate electrode 12 with layer resistance 15 Ω/hole, source and drain regions 10, 1 with layer resistance 10/hole at junction depth 1.5 μm
3. After forming the SiO ₂ film 19 with a thickness of 4000 Å, a film with a thickness of 5000 Å and a layer resistance of 30
A second polycrystalline silicon electrode 14 of Ω/hole is formed. Furthermore, an insulating film 16, a film thickness of 5000 Å, and a layer resistance of 15
forming a third polycrystalline silicon electrode 15 of Ω/mouth;
8000Å thick phosphor glass ( _P2O5 concentration _2mole %)
After depositing Al 9, a contact hole 17 is formed and Al
Electrodes 41 are formed. Note that in FIGS. 1 and 2, the second polycrystalline silicon 14, the insulating film 1
6. The third polycrystalline silicon 15 constitutes a storage capacitor. Further, in this case, the insulating film 16 is
A large storage capacity can be obtained by using, in addition to the SiO ₂ film, a film with a high dielectric constant such as a Si ₃ N ₄ film or a Ta ₂ O ₅ film, or a multilayer insulating film that is a combination of these films. Therefore, in order to obtain the same storage capacitance value as that used in conventional memory cells, the area required is smaller. For example, 800Å as an insulating film.
When using SiO ₂ film, Si ₃ N ₄ film, Ta ₂ O ₅ film, contact hole size is 2 μm, mask alignment margin is 2 μm, polycrystalline silicon gate width is 6 μm, impurity doped layer (diffusion layer) width is 6 μm, storage capacity Assuming 0.22pF, the memory cell area per bit is 725μm ² and
297μm ² and 192μm ² . This area is the area of conventional memory cells manufactured using the same design values.
78%, 32%, and 21% of ^925μm2 .

Writing and reading information to and from the memory cell shown in this embodiment is performed as follows. That is, the third
After fixing polycrystalline silicon electrode 15 to the ground potential, switching transistor 1 is made conductive by applying a positive voltage to word line 31 made of first polycrystalline silicon. Thereafter, by applying a voltage corresponding to "0" or "1" to the data line 41 made of Al, charges serving as information are stored in the storage capacitor 2. To read information, after turning on the switching transistor 1, the data line 41 is
This is done by detecting changes in the potential of In the memory cell of the present invention, since an inversion layer is not used to form a storage capacitor, no leakage current flows due to the inversion layer. Therefore, there is an advantage that the storage information retention time becomes significantly longer.

FIGS. 5 and 6 show a plan view and a cross-sectional view (for 2 bits of memory cells) of another embodiment of the present invention. As can be seen from the figure, in this example,
Contact holes 18 and 17 for bringing the impurity doped regions (diffusion regions) 10 and 13 into contact with the second polycrystalline silicon electrode 14 and Al electrode 41 are formed in a self-aligned manner. The formation of contact holes by such self-alignment is described in detail in Japanese Patent Application No. 111622/1982, previously filed by the present inventors.

By employing a self-aligned contact method, the advantages of using the present invention become even more pronounced. For example, as the insulating film 16, an 800 Å SiO ₂ film, Si ₃ N ₄
When the memory of this example is manufactured using a Ta ₂ O ₅ film and a Ta 2 O 5 film based on the above-mentioned design values, the memory areas will be 675 μm ² , 275 μm ² , and 176 μm ² , respectively. These areas are 73%, 29%, and 19%, respectively, of the conventional memory cell area of 925 μm ² fabricated using the same design values.

FIGS. 7 and 8 show a plan view and a sectional view of another embodiment of the present invention (for 2 bits of memory cells). In this example, as shown in the figure, element isolation in the X direction (data line direction) is performed using an 800 Å SiO ₂ film 2
This is done by applying a negative voltage to the first polycrystalline silicon 20 formed on the first polycrystalline silicon 20 (referred to as fielded shield). Field shielding methods have already been described in detail in the known literature. Self-aligning contacts and field
By employing a shielding method, the advantages of using the present invention become even more pronounced. In other words, changes in contact hole dimensions due to lateral oxidation (bird's beak), which occur when forming an oxide film for element isolation by local oxidation, and crystal defects at the edges of the oxide film for element isolation, etc. Leakage currents are reduced and self-aligned contact methods are facilitated.

With this configuration, the conductive film 14 made of polycrystalline silicon has substantially vertical side walls facing each other when viewed in cross section, and the height of the side walls is equal to or smaller than the height of the conductive film 14. The storage capacitance value can be increased in this portion.

Regarding the memory cell area, it is almost the same as in the cases of FIGS. 5 and 6. In FIGS. 3 to 8, the second polycrystalline silicon 14, the insulating film 16, and the third polycrystalline silicon 15 constituting the storage capacitor 2 can be processed by self-aligned etching without requiring a mask alignment margin.

〔Effect of the invention〕

As explained above, according to the present invention, since a part of the storage capacitor is provided so as to overlap with the top of the switching transistor, the memory cell area can be significantly reduced compared to conventional semiconductor memory, and the degree of integration of semiconductor memory can be increased. It can be significantly improved. Unlike the conventional one-transistor type MOS memory, the semiconductor memory device according to the present invention has the advantage that the information retention time is significantly longer because there is no leakage current due to the inversion layer induced to form the storage capacitor. There is.

[Brief explanation of the drawing]

1 and 2 are a plan view and a sectional view showing an embodiment of the present invention, respectively, and FIG. 3 is a conventional one.
A plan view of a 1-bit transistor type MOS memory cell, FIG. 4 is a cross-sectional view thereof, FIGS. 5 and 7 are plan views of a 2-bit MOS memory cell according to the present invention, and FIGS. 6 and 8 are cross-sectional views thereof. It is. 1: Switching transistor, 2: Storage capacitor, 3: Word line (Al line), 4: Data line (diffusion layer), 5: Silicon substrate, 6: Oxide film for isolation between elements, 7: Gate oxide film, 8 : first polycrystalline silicon electrode, 9: interlayer insulating film (phosphorus glass), 10,1
3: Diffusion layer, 11: Inversion layer, 12: First polycrystalline silicon gate electrode, 14: Second polycrystalline silicon, 15: Third polycrystalline silicon, 16: Insulating film for forming storage capacitor, 17, 18, 22: Contact hole, 19: Interlayer oxide film, 20: First polycrystalline silicon for field shield, 21: Oxide film for field shield, 31: Word line (first polycrystalline silicon), 41: Data line (Al line) .

Claims (1)

[Claims] 1. A semiconductor having a plurality of word lines, a plurality of data lines provided to intersect with the word lines, and a plurality of memory cells provided at the intersections of the word lines and the data lines. In the device, the memory cell includes a capacitor for storing information and a switching transistor for controlling reading and writing of information to the capacitor, and the switching transistor includes a gate insulating film, a gate electrode, a source region, and a switching transistor. , a drain region, and the capacitor includes a first conductive film, a capacitive insulating film provided on the first conductive film, and a second conductive film provided on the capacitive insulating film. The capacitive insulating film is a multilayer insulating film, and the first conductive film extends from above the element isolation insulating film so that an end thereof is located on the gate electrode, and The first conductive film is electrically connected to one of the source and drain regions, the data line is electrically connected to the other of the source and drain regions, and the plurality of Of the memory cells, two adjacent memory cells share the other of the source region and drain region electrically connected to the data line, and the gate electrode of the switching transistor is connected to the word line. A semiconductor device, wherein the data line is electrically connected to a line, and the data line is provided on the second conductive film with an interlayer insulating film interposed therebetween. 2. The semiconductor device according to claim 1, wherein the capacitive insulating film contains SiO ₂ . 3. The semiconductor device according to claim 1 or 2, wherein the capacitive insulating film contains Si ₃ N ₄ . 4. The semiconductor device according to any one of claims 1 to 3, wherein the capacitive insulating film contains Ta ₂ O ₅ . 5. The semiconductor device according to claim 1, wherein the first conductive film contains polycrystalline silicon. 6. The semiconductor device according to claim 1, wherein the second conductive film contains polycrystalline silicon. 7. Claims 1 to 6, characterized in that a ground potential is applied to the second conductive film.
The semiconductor device according to any one of paragraphs. 8. Claim 1, wherein the semiconductor device is a random access memory.
The semiconductor device according to any one of Items 7 to 7. 9. In a semiconductor device having a plurality of word lines, a plurality of data lines provided to intersect with the word lines, and a plurality of memory cells provided at the intersections of the word lines and the data lines, the memory cell includes a capacitor for storing information and a switching transistor for controlling reading and writing of information to the capacitor, and the switching transistor has a gate insulating film, a gate electrode, a source region, and a drain region. The capacitor includes a first conductive film, a capacitive insulating film provided on the first conductive film, and a second conductive film provided on the capacitive insulating film, The first conductive film extends from above the element isolation insulating film so that its end is located on the gate electrode, and the first conductive film extends from one of the source region and the drain region. The data line is electrically connected to the other of the source region and the drain region, and two adjacent memory cells among the plurality of memory cells are electrically connected to the data line. The other of the electrically connected source and drain regions is shared, the gate electrode of the switching transistor is electrically connected to the word line, and the first conductive film has a cross section. A semiconductor device having substantially vertical side walls facing each other when viewed from above, the height of the side walls being higher than the thickness of the first conductive film. 10. The semiconductor device according to claim 9, wherein the capacitive insulating film contains SiO ₂ . 11. The semiconductor device according to claim 9 or 10, wherein the capacitive insulating film contains Si ₃ N ₄ . 12. The semiconductor device according to any one of claims 9 to 11, wherein the capacitive insulating film contains Ta ₂ O ₅ . 13. The semiconductor device according to any one of claims 9 to 12, wherein the capacitive insulating film is a multilayer insulating film. 14 Claims 9 to 1, wherein the first conductive film contains polycrystalline silicon.
The semiconductor device according to any one of Item 3. 15 Claims 9 to 1, wherein the second conductive film contains polycrystalline silicon.
The semiconductor device according to any one of Item 5. 16. The semiconductor device according to any one of claims 9 to 15, wherein a ground potential is applied to the second conductive film. 17 The above semiconductor device has random access
17. The semiconductor device according to claim 9, wherein the semiconductor device is a memory.