JPS63115370A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a strong resistance to soft errors by providing an insulating film between the p-type high impurity concentration regions and the n-type high impurity concentration regions so as to prevent the p-type high impurity concentration regions and the n-type high impurity concentration regions from being directly contacted, thereby making the capacity of the charge storing region large without lowering the pn junction dielectric strength. CONSTITUTION:An oxide film 5 is provided under s source 3 and a drain 4 regions, and below it p-type high impurity concentration regions 7, 8 are provided. Since the oxide film 5 is interposed between the source and drain regions 3, 4 and the p-type high impurity concentration regions 7, 8 and they are not directly contacted with each other, the p-n dielectric strength depends on the dielectric breakdown strength of the oxide film 5 rather than the impurity concentration, so the impurity concentration of the p-type regions 7, 8 can be made high. If such MOS transistor is used as the driver MOS of a static type random access memory, due to a large capacity of the charge storing region and a small efficiency of collecting noise charges, the reduction amount of the drain potential due to the carriers induced by alpha-rays or the like becomes small, providing a strong resistance to soft errors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that is less likely to malfunction due to carriers induced by alpha rays or the like.

[Conventional technology]

As microfabrication technology advances, memory cells are becoming increasingly finer. Along with this, the amount of accumulated charge in memory cells decreases, and soft errors, in which information is destroyed by noise charges induced by alpha rays, etc., have become a problem.

In order to solve the problem of soft errors, conventional methods have been used, for example, in Japanese Patent Application Laid-Open No. 113462/1983 and Japanese Patent Application Laid-open No. 59-84.
As described in Japanese Patent No. 461, a p-type high impurity concentration region is provided adjacently below the n-type high impurity concentration region serving as a charge storage region to increase the junction capacitance and connect the p-type substrate and the p-type substrate. There is a method in which the efficiency with which noise charges gather at the junction is reduced by a potential barrier between the mold cavity and the impurity concentration region. The larger the capacitance value, the smaller the amount of change in potential when the same amount of noise charge flows in. Also, if the efficiency of charge collection becomes smaller, the amount of charge flowing in will decrease. , the occurrence of soft errors is suppressed.

[Problem that the invention seeks to solve]

The above conventional technology is currently the most widely used technology. In order to further suppress the occurrence of soft errors using the above-mentioned conventional technology, it is necessary to further increase the impurity concentration in the p-type cavity impurity concentration region. However, if the n-type and p-type regions are in contact with each other at a high concentration, the avalanche breakdown voltage of the junction decreases, so the upper limit of the n-type impurity concentration is determined by the junction breakdown voltage standard. The impurity concentration of the n-type region is generally lXl0
If the p-n junction is a step junction and the junction breakdown voltage is IOV, the upper limit of the impurity concentration in the P-type head region is approximately 1×1017■-8.At this time, the junction capacitance is Ov. When the impurity concentration of the n-type substrate is 1×1014 mark -8, the potential barrier becomes about 180 m e v.With the above conventional technology, no further effect can be obtained, and further miniaturization is required. The present invention aims to provide a semiconductor device that is resistant to soft errors by increasing the capacitance of the <-1 charge storage region.

[Means for solving problems]

The above purpose is to provide an insulating film between the n-type high impurity concentration region and the n-type high impurity concentration region, and to
This is achieved by ensuring that the high impurity concentration regions of the mold do not come into direct contact with each other.

[Effect]

Since an insulating film is interposed between the p-type high impurity concentration region and the n-type high impurity concentration region, the pn breakdown voltage is determined by the dielectric breakdown strength of the insulating film, regardless of the impurity concentrations of both. Therefore, if this insulating film is made to have a thickness that provides a predetermined dielectric strength or higher, the concentration of n-type impurities can be increased without lowering the p-n dielectric strength. This pn capacitance can be regarded as a series connection of the capacitance of the insulating film and the capacitance of the depletion layer. Assuming that the concentration of n-type impurities is sufficiently higher than that of n-type impurities, and the depletion layer hardly extends into the n-type region, but only in the n-type region, the higher the impurity concentration in the n-type region, the more The depletion layer width becomes narrower,
The capacitance value approaches that of the insulating film alone. Therefore, it is desirable to make the insulating film as thin as possible. The higher the impurity concentration in the n-type region, the higher the capacitance, the higher the potential barrier between the n-type region and the substrate, and the lower the efficiency of collecting noise charges, making it more resistant to soft errors.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a cross-sectional view of a Mos+-run lister according to the present invention. 1 is a gate electrode, 2 is a gate oxide film, 3 is a source region, and 4 is a drain region. An oxide film 5 is provided below the source and drain regions, and further below, n-type high impurity concentration regions 7 and 8 are provided.

In this structure, for example, an oxide film 5 is selectively formed on the surface of an n-type substrate 9, and n-type impurities are ion-implanted through the oxide film 5 to form a p-type high impurity concentration region, and the entire surface is covered with polycrystalline silicon. is deposited and recrystallized by laser annealing, the surface is oxidized to form gate oxide film 2, gate electrode 1 is formed from polycrystalline silicon, n-type impurity is ion-implanted using gate electrode 1 as a mask, and heat treated. This can be realized by diffusing the n-type region to the oxide film 5. The channel region directly under the gate electrode is recrystallized using the P-type substrate as a seed, so good crystals are obtained and the MOS
The characteristics of the transistor also become good. Further, since the same n-type region can be obtained by using polycrystalline silicon, there are various other manufacturing methods. The source/drain regions 3 and 4 and the n-type high impurity concentration regions 7 and 8 are interposed through the oxide film 5 and are not in direct contact, so the pn breakdown voltage is determined by the dielectric breakdown strength of the oxide film 5 regardless of the impurity concentration. ,n
The impurity concentration of the mold regions 7 and 8 can be increased. The impurity concentration of the source/drain regions 3 and 4 is I x 10
”an-8t The impurity concentration of n-type regions 7 and 8 is 1×10
19■-3v The impurity concentration of the P-type substrate 9 is lXl0''■
-8. Assuming that the thickness of the oxide film 5 is 200, the minimum value of the capacitance between the source/drain regions 3 and 4 and the n-type regions 7 and 8 is 1.5 f F/μm', and the n-type substrate 9 and The potential barrier between n-type regions 7 and 8 is 300 m e V
The capacitance is 1.5 compared to the case without the oxide film 5.
more than double, the potential barrier becomes 1.7 times. Oxide film 5
If the capacitor is made of a silicon nitride film with a higher dielectric constant, the capacitance will be further increased.

If this MOS transistor is used as the driver MO8 of a static type non-access memory, the capacitance of the charge storage region is large and the efficiency of collecting noise charges is low. becomes smaller and more resistant to soft errors.

FIG. 2 shows a second embodiment of the invention. The difference from the first embodiment is that the oxide film 5 is provided only under the drain region 4. The drain of the driver MO8 of the high-resistance static random access memory is connected to the power supply potential via the gate of the other driver MO8, whose drain and gate are cross-connected to each other, and a high resistance, and charges are transferred to this region. accumulate. On the other hand, the source region is grounded using a low resistance wiring material. Therefore, even if noise charges flow into the source region, the potential does not change. In FIG. 2, below the drain region 4 is an oxide film 5 and a p-type high impurity concentration region 8.
is provided to increase the capacitance and reduce the efficiency of collecting noise charges.The source region 3 has only an n-type diffusion layer, making the efficiency of collecting noise charges higher than that of the drain, so that the noise type charges Since it is made easier to collect in the source, soft error tolerance is further increased.

Further, by using the MOSFET according to the present invention only in the memory cell portion where a large capacity is desired and by using the conventional structure in the peripheral circuit portion where a small capacity is desired, it is possible to obtain a memory with high speed and high soft error tolerance.

FIG. 3 shows a third embodiment of the present invention. FIG. 3 is an example in which the present invention is applied to a dynamic random access memory. Noise charges are less likely to flow into the charge storage region 3, the capacitance increases, and the amount of stored charge increases, making it resistant to soft errors.

〔Effect of the invention〕

According to the present invention, the storage capacitance can be increased without lowering the withstand voltage, and the efficiency of collecting noise charges generated by α rays can be reduced, so that a semiconductor device with high soft error tolerance can be provided.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a MOS transistor according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a MOS transistor according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a MOS transistor according to a third embodiment of the present invention. FIG. 2 is a cross-sectional view of a memory cell of a dynamic random access memory. 1... Gate electrode, 2... Gate insulating film, 3...
Source region, 4... Drain region, 5... Insulating film,
6... Field oxide film, 7... P type high impurity concentration region, 8... P type high impurity concentration region, 9... P type substrate, 10... Capacitor electrode.

Claims (1)

[Claims] 1. A semiconductor region of a second conductivity type provided in a semiconductor region of a first conductivity type; an insulating film provided adjacently below at least a portion of the semiconductor region of the second conductivity type; A semiconductor device comprising a first conductivity type semiconductor region having a higher impurity concentration than the first conductivity type semiconductor region provided below and adjacent to the film.