JPS62112359A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the step-cut of the wiring of a gate array by a method wherein a protruded part of an insulating film between devices is flattened and a a by-pass capacitor is formed simultaneously with the gate of an MOS transistor. CONSTITUTION:Si oxide films 2 and Si nitride films 3 are formed on the surface of a P-type Si substrate 1. Then a field oxide film 4 is formed and the film 3 is removed and resist 5 is applied. Then the whole surface is etched and flattened. After that, gate oxide films 6 are formed and polycrystalline Si 7 doped with high concentration phosphorus is deposited by CVD and patterned to form the gate electrodes and the electrode of the by-pass capacitor of an MOS transistor are formed. Then N<+>type source and drain 8 are formed and two wiring layers 11 and 12 are formed on oxide films 9 and 10 respectively with the oxide film 10 between the layers 11 and 12. With this constitution, as an earth capacitance is large, patterning of the capacitor electrode is eliminated so that the step-cut of the wiring of a gate array can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an integrated circuit device in which a capacitor is formed under a wiring area and a bypass capacitor is built in.

[Technical background of the invention and its problems]

In the past, elements have been integrated in response to miniaturization, but few measures have been taken to counteract noise in the power supply, and the method used is to attach a single capacitor outside the gate array. Therefore, circuits using gate arrays required space for capacitors on the board.

Therefore, it is important to form a bypass capacitor inside the gate array.

However, when it is formed on a field oxide film as shown in Figure 2, the capacitance to ground is too small, and if the patterning is modified as shown in Figure 3, the flatness of the wiring area is lost and the wiring is broken. There was a problem with the storage.

[Purpose of the invention]

An object of the present invention is to equip a gate array with a bypass capacitor before a master slicing process without impairing the flatness of the wiring area.

[Summary of the invention]

Usually, a master slice type integrated circuit device is formed of an element region (42) and a wiring region (43) as shown in FIG. 4, but the wiring region is used only for metal wiring. Therefore, by forming eight capacitors under the wiring area and connecting the capacitance between the power supplies, it is used as a bypass capacitor for the integrated circuit device. Form a bypass capacitor at the same time as the gate.

〔Effect of the invention〕

According to the present invention, as shown in Figure @5, a bypass capacitor is built in, and the noise from the source is absorbed by the bypass capacitor, making it possible to control malfunctions without increasing the area of the integrated circuit.

According to the present invention, since the capacitance to ground is large, patterning of the capacitor electrode is not required, and this is effective in preventing disconnection of wires in the gate array.

[Embodiments of the invention]

Examples are shown in FIGS. 1(a) to (θ). First, a silicon oxide film ■ and a silicon nitride film ■ are deposited on the surface of a P-type silicon substrate.
(Figure 1a). Next, thermal oxidation is performed at 1000° C. to form a field oxide film with a thickness of 1 μm (b), the silicon nitride film (2) is removed, and a resist (2) is applied (e).

Next, resist/S x O is removed by reactive ion etching.
The entire surface is etched at the same etching speed as a to make it flat. After that, a gate oxide film ① is formed, polycrystalline silicon ② doped with a high concentration of phosphorus is formed by CVD, and patterned to form a gate electrode of a MOS transistor and an electrode of a capacitor for a bypass capacitor (d). Mouth+
The source and drain are formed, and finally the Al 12 layer wiring (11) (
12). At this time, although not shown in FIG. 9, contact is also made to the electrode of the bypass capacitor.

[Brief explanation of drawings]

FIGS. 1(a) to (s) are process cross-sectional views of an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views of a comparative example, FIG. 4 is a plan view of the gate array, and FIG. FIG. 2 is a circuit diagram showing a bypass capacitor. Agent Patent Attorney Noriyuki Ken Yudo Takehana Kikuo (d) Figure l Figure 2 Figure 3

Claims (1)

[Claims] A step of selectively oxidizing the field region of the semiconductor substrate to form an element isolation insulating film, a step of etching the main surface portion of the substrate of the element isolation insulating film to planarize the substrate, and a step of forming a MOS transistor in the element region. A method of manufacturing a semiconductor device, comprising the steps of forming a gate electrode and forming a capacitor electrode for a bypass capacitor in a field region.