JPS5828737B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an improvement in its multilayer wiring system.

As semiconductor devices become more highly integrated, not only patterns become finer, but also large amounts of conductive and insulating films are used.
Semiconductor integrated circuits have begun to be manufactured.

For example, using two layers of polycrystalline silicon, N-channel MO8
LSI is being manufactured.

FIG. 1a"e is a cross-sectional view at each stage for explaining a conventional method for forming two polycrystalline silicon layers constituting a gate electrode in such a case.

First, as shown in FIG. 1a, a first gate oxide film 2 is formed on a P-type semiconductor substrate 1, and this first gate oxide film 2 is
A first polycrystalline silicon layer 3 is formed thereon.

Next, as shown in FIG. 1, a portion of the first polycrystalline silicon layer 3 and the first gate oxide film 2 are removed by photolithography.

Next, as shown in FIG. 1C, a second gate oxide film 4 is formed on the first polycrystalline silicon layer 3 and on the exposed surface of the P-type semiconductor substrate 1. A second polycrystalline silicon layer 5 is formed thereon.

Next, as shown in FIG. 1d, the second polycrystalline silicon layer 5 and a portion of the second gate oxide film 4 are removed by photolithography.

Next, as shown in FIG. 1e, a protective oxide film 6 is formed on the exposed surface of the first polycrystalline silicon layer 3 and on the second polycrystalline silicon layer 5. removing the protective oxide film 6 at a predetermined position on the second polycrystalline silicon layer 5;
A first gate electrode 7 and a second gate electrode 8 are formed.

In such a structure, for example, one memory element is composed of a MOS transistor having the second polycrystalline silicon layer 5 as a gate and a capacitor having the first polycrystalline silicon layer 3 as one electrode and the semiconductor substrate 1 as the other electrode. This is effective for reducing the area on a semiconductor chip such as the storage element of the dynamic random access memory that constitutes the dynamic random access memory. Due to poor coverage of the 2-gate oxide film 4, Fig. 1e
Insulation failures often occurred between the edge of the first polycrystalline silicon layer 3 shown by the arrow in FIG.

The present invention aims to improve this point.

That is, while keeping the thickness of the second gate oxide film 4 on the P-type semiconductor substrate 1 the same as that of the conventional film, the edges of the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5 are lower τ
By increasing the distance between the edge of the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 50,
This is intended to prevent poor insulation between the bottom corner and the bottom corner.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIGS. 2a"'-e are cross-sectional views at various stages for explaining a method of forming a two-layer polycrystalline silicon gate interconnection portion as an embodiment of the present invention.

First, as shown in FIG. 2a, a first
A gate oxide film 2 is formed, a first polycrystalline silicon layer 3 is formed on this first gate oxide film 2, and an intermediate oxide film 9 is further formed on this first polycrystalline silicon layer 3.

Next, as shown in FIG. 2, a part of the intermediate oxide film 9 is removed by photolithography, and the first polycrystalline silicon layer 3 and the first gate oxide film 2 are removed from the area where the intermediate oxide film 9 has been removed. Needless to say, the remaining intermediate oxide film 9 is penetrated to the inside and removed.

This is then subjected to thermal oxidation to form a second gate oxide film 4 on the oxide film 9, on the exposed surface of the P-type semiconductor 1, and on the first polycrystalline silicon layer 3, as shown in FIG. Formed on the etched end surface.

Since the thermal oxidation method is used as described above, the oxide film formation rate is different between the top of the oxide film and the other parts, and the second gate oxide film 4 is formed more easily on the intermediate oxide film 9 than on other parts. The first polycrystalline silicon layer 3 is formed to be thin, and furthermore, the end face of the first polycrystalline silicon layer 3 under the eaves-like portion of the intermediate oxide layer 9 is easily subjected to thermal oxidation, so the first polycrystalline silicon layer 3 is formed to have a sufficient thickness.

Further, a second polycrystalline silicon layer 5 is formed on the second gate oxide film 4 by, for example, a low pressure CVD method.
As shown in FIG. d, parts of the second polycrystalline silicon layer 5, second gate oxide film 4, and intermediate oxide film 9 are removed by photolithography to expose the first polycrystalline silicon layer 3.

Next, as shown in FIG. 2e, a protective oxide film 6 is formed on the exposed surface of the first polycrystalline silicon layer 3 and on the second polycrystalline silicon layer 5.
The protective oxide film 6 at predetermined positions on the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5 is removed, and a first gate electrode 7 and a second gate electrode 8 are formed.

FIG. 3 is a cross-sectional view showing an N-channel MO3 field effect transistor to which the present invention is applied. In the figure, 10 is a field oxide film, 11, 12 are N-type diffusion regions, 13,
Reference numeral 4 designates electrodes to these diffusion regions 11 and 12.

The other two-layer polycrystalline silicon gate portion has the structure of the present invention explained in FIG.

In such a structure, the thickness of the second gate oxide film 4 on the P-type semiconductor substrate 1 is the same as that of the conventional one shown in FIG. Since the distance between the bottom corner of the crystalline silicon layer 50 and the lower surface corner can be increased, it is possible to prevent insulation defects from occurring even though the coverage of the second gate oxide film 4 is incomplete.

In the above embodiments, the case was described where the application was applied to a multilayer polycrystalline silicon gate electrode of an N-channel MO8 field effect transistor. In addition to the oxide film, general insulators such as silicon nitride and alumina can be used, and the polycrystalline silicon layer can generally be a polycrystalline semiconductor layer, or may be a single crystal semiconductor layer.

Furthermore, it can be applied not only to field effect transistors but also to multilayer wiring structures.

As described in detail above, in the present invention, a first semiconductor layer is formed on a part of one principal surface of a semiconductor substrate with a first insulating film interposed therebetween, and In the structure in which a second semiconductor layer is formed over the remainder of the main surface of the semiconductor substrate via a second insulating film, an eave-like layer is formed on the first semiconductor layer above the remainder of the main surface of the semiconductor substrate. Since it has a structure in which the above-described second insulating film and second semiconductor layer are provided after providing the extending intermediate insulating film, a sufficient insulating distance can be maintained between the first and second semiconductor layers, The occurrence of insulation defects is prevented.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 a"e is a cross-sectional view at each stage for explaining the method of forming a conventional device, and Fig. 2 a"e is a two-layer polycrystalline silicon film as an embodiment of the present invention. FIG. 3 is a cross-sectional view of an N-channel MO8 type field effect transistor to which the present invention is applied. In the figure, 1 is a semiconductor substrate, 2 is a first insulating film, 3 is a first semiconductor layer, 4 is a second insulating film, 5 is a second semiconductor layer, and 9 is an intermediate insulating film. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first insulating film formed on a part of the whole surface of a semiconductor substrate, a first semiconductor layer formed on this first insulating film, and a first semiconductor layer formed on this first insulating film. an intermediate insulating film formed thereon and extending in an eave-like manner above the remainder of the main surface of the semiconductor substrate; 1. A semiconductor device comprising: a second insulating film formed on the remaining portion; and a second semiconductor layer formed continuously on the second insulating film. 2. The semiconductor device according to claim 1, wherein polycrystalline semiconductor layers are used for the first and second semiconductor layers. 3. The semiconductor device according to claim 1, wherein a single crystal semiconductor layer is used for the first and second semiconductor layers.