JPS62111443A - Composite semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the parasitic capacitance and the capacitance deviation in a composite semiconductor device, by forming a series of a P-N junction isolating SOI (Silicon on Insulator) structure and a P-N junction capacitor in a second semiconductor substrate which is provided on a first semiconductor substrate through an insulating film. CONSTITUTION:A composite semiconductor device 10 employs a substrate 4 in which a P-type second semiconductor substrate 3 is laminated on a first semiconductor substrate 1 through an insulating film 2. An N-type semiconductor layer 5 is formed in the specified region of the substrate 3. In the N-type semiconductor layer 5, an N<+> layer 6 which is an element is formed. On the main surface of the substrate 3, an insulating film 7 is formed. On the insulating film 7, a wiring layer 8 having a specified pattern which is connected to the N<+> layer or the N-type semiconductor layer 5 through a contact hole is formed Owing to the structure of the substrate 4 of this composite semiconductor device 10, the capacitor formed with the back surface becomes the series of the so- called SOI structure and the capacitance at a P-N junction, and the capacitance can be strikingly reduced.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a composite semiconductor device.

[Technical background of the invention and its problems]

Conventionally, PN junction isolation using a PN junction has been used to isolate complex elements of a complex semiconductor device.

However, the following problems 6. Ta.

(Because the parasitic capacitance caused by the PN junction is too large,
This is a factor that deteriorates high frequency characteristics.

Gu Xi II-De You Intrusion Le Small Buddha Spring Liao Gong 4 Funada PN
A so-called capacitance deviation occurs due to the junction, which changes the characteristics of the series integrated element.

[Purpose of the invention]

An object of the present invention is to provide a composite semiconductor device in which the parasitic capacitance of an integrated element is reduced and the capacitance deviation is reduced.

[Summary of the invention]

The present invention provides a P N junction isolation structure on a second semiconductor substrate provided on a first semiconductor substrate with an insulating film interposed therebetween to form a so-called SOI
r) This is a composite semiconductor device in which the parasitic capacitance of the integrated element and the capacitance deviation are reduced by configuring a series of structures and PN junction capacitances.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to a twin Schottky diode.

This composite semiconductor device uses a substrate 4 in which a P-type second semiconductor substrate 3 is laminated on a first semiconductor substrate 1 with an insulating film 2 interposed therebetween as shown in FIG. Second semiconductor substrate 3
An N-type semiconductor layer 5 of the opposite conductivity type is formed in a predetermined region of . The surface concentration of the N-type semiconductor layer 50 is set to 3XLOcm or more so that a Schottky junction can be formed. Further, the resistivity of the second semiconductor substrate 3 is 3
It is set to 0Qcm or more. In the N-type semiconductor layer 5,
An element element N16 is formed. An insulating film 7 is formed on the main surface of the second semiconductor substrate 3 including the N+ layer 6 and the N-type semiconductor layer 5. The insulating film 7 includes an N layer 6. Contact holes communicating with each of the N-type semiconductor layers 5 are opened. On the insulating film z, N is applied via a contact hole.
A wiring layer 8 having a predetermined pattern connected to the layer 6 or the N-type semiconductor layer 5 is formed. The wiring layer 8 is made of Mo/AL! After the ivy was deposited, it was formed into a predetermined shape by photo-etching.

The composite semiconductor device 10 configured in this manner is as follows.

Since the substrate 4 has the structure shown in FIG. 1, the capacitance with the back side becomes a series of capacitances of a so-called SOI structure and a PN junction, and can be significantly reduced. Incidentally, it has been confirmed that the capacitance can be reduced to about 3/4 of that of a conventional composite semiconductor device using PN junction isolation.

In another embodiment of the present invention, the second semiconductor substrate 3 is etched to form an island region 3a for each element.

The wiring layer 8 forms an island region 5theJb, forming a twin Schottky diode with complete insulation isolation.
A padding pad may be provided on top to prevent breakage.

In this case, the area of the island regions 3g and 3b is half of that of the above embodiment, so the MO8 capacitance in this part is reduced and the inter-element capacitance is reduced to 2/3 of that in the conventional PN junction isolation.
can be reduced to a certain degree.

It goes without saying that the present invention can be applied not only to twin Schottky diodes but also to composite elements such as diodes and transistors, and integrated elements.

〔Effect of the invention〕

As described above, the composite semiconductor device according to the present invention has remarkable effects such as reducing the parasitic capacitance of the integrated element, reducing the container deviation, and improving high frequency characteristics.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing a substrate structure used in an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a schematic configuration of one embodiment of the present invention, and FIG. 3 is an explanatory diagram showing another embodiment of the present invention. FIG. 2 is an explanatory diagram showing a schematic configuration of an example. l... first semiconductor substrate, 2... insulating film, 3... second semiconductor substrate, 4... substrate, 5... N-type semiconductor layer,
6... N+ layer, 7... Insulating film, 8... Wiring layer, I
n, - composite semiconductor device. Applicant's representative Patent attorney Takehiko Suzue Figure 1, Figure 1, Figure 2, Figure 3

Claims (1)

[Claims] a second semiconductor substrate formed on the first semiconductor substrate via an insulating film; a plurality of semiconductor layers of opposite conductivity types formed in a predetermined region of the second semiconductor substrate; and a plurality of semiconductor layers formed within the semiconductor layer. What is claimed is: 1. A composite semiconductor device comprising: an element element;