JPS62110328A - Musical interval restoring device - Google Patents

Abstract

PURPOSE:To obtain the titled device where the missing of information after the restoration of musical interval is less and noise at a connecting point is reduced by providing the 2nd read number generating circuit, the 2nd holding circuit, the 1st and 2nd multiplier circuits, an adder circuit and an amplitude control circuit. CONSTITUTION:The output signals of the 1st and 2nd multiplication circuits 6, 7 become an analog output respectively via the 1st and 2nd integration circuits 16, 17, and the outputs of the 1st and 2nd integration circuits 16, 17 are outputted to an adder circuit 8. 1-Bit DA conversion circuits 26, 27 convert a digital signal from a digital memory into an analog signal. The amplitude control is applied by using an amplitude control circuit 9 so as to change the multiplication coefficient of the 1st and 2nd multiplication circuits 6, 7 to 0-1 in response to the output of the 1st and 2nd holding circuits 4, 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pitch restoring device that restores the pitch of a sound to the same pitch as when it was recorded when an audio signal is played back at twice the recording speed.

2. Description of the Related Art In recent years, it has become important to reproduce audio signals at a speed different from the recording speed. If you play back at twice the recording speed,
It takes half the time it would normally take, and allows you to understand the content recorded on a tape recorder or VTR in half the time. but,
If you simply double the playback speed, the pitch will not be high enough.
It becomes difficult to hear, and at the same time, the characteristics of the speaker are not highlighted.

Therefore, there is a need for a device that can quickly listen to recorded content in a short time without changing the pitch of the sound.

(Example: Eva, ``Compressing and expanding the time axis of conversation 7'l
/″-da” Nikkei Electronics 1976-7° and below,
A conventional pitch restoring device will be explained with reference to the drawings.

FIG. 8 shows a configuration diagram of a conventional pitch restoring device. In FIG. 8, 1 is an analog-to-digital conversion circuit that converts a digital signal into a digital signal, 2 is a digital memory that stores the digital signal, and 3 is a write/read control circuit that controls writing and reading from the digital memory 2. 4 is a holding circuit that holds the signal read out from the digital memory 2; 16 is a digital-analog conversion circuit that converts the digital signal output from the holding circuit 4 into an analog signal; 10 is the analog-digital conversion circuit 1; 11 is a write address generation circuit that supplies the address to be written in the digital memory 2 to the write/read control circuit 3; 12 is a circuit that supplies the address to be read from the digital memory 2 to the write/read control circuit 3; Read address generation circuit, 14
1 is a demodulation clock generation circuit that operates the digital-to-analog conversion circuit 16, and 15 is a low-pass filter.

The operation of the pitch restoring device configured as described above will be described below. Fig. 9 shows a diagram of its principle. Time if you want to play it back at the same speed it was recorded.

<t2NT, d0, dI' + with period 2T
”...+dN--1 N signals are reproduced.

At this time, in double speed playback, 0≦t (at 2NT,
do, d4. ...+d2N-j signal is reproduced. In order to lower the pitch and make it the same pitch as when recording, as shown in Figure 9(d), 0 <
1 <2NT d0, dl + scream”r
Regenerate dN-1, dN, dN+1.・・・・・・
, d2N−+ signals are not regenerated, and 2NT≦t(
4NT is d2N+ d2N+1 +・・・・・・,
Play 63N-1. The following will be played in the same manner.

This restores the reproduced signal to its original pitch at the time of recording.

Problems to be Solved by the Invention However, in the above method, the signal is discontinuous between dN~1 and 62N, and noise occurs.
The signal of dN+l+...+d2N-1 is not reproduced at all, and there is a problem in that the information of this part of the signal is lost. In addition, if N is made small in order to avoid missing signals over a long period of time, the number of connection points per time increases and noise increases.

In view of the above-mentioned problems, the present invention provides a pitch restoring device that uses all input signals and processes discontinuous points, thereby reducing missing information and reducing noise at connection points. be.

Means for solving the problem In order to achieve this object, the pitch restoring device of the present invention converts an analog input signal into a 1-bit digital signal and outputs it to a digital memory for storing this digital signal. A digital conversion circuit, a write address generation circuit, and a first . a write/read control circuit that uses address data generated by the second read address generation circuit as input data to designate a write/read address in the digital memory and generates a write/read control signal; The first . For each signal bordered by the second holding circuit and the first and second holding circuits, a monotonically increasing weighting function L (X) (σx≦NT, O≦W, (X )≦
1) or a monotonically decreasing weight function W2(x), (0
fXKNT, O'-W2CX)'='). a second multiplier circuit, an amplitude control circuit that controls the first and second multiplier circuits, and a digital output signal of the first and second multiplier circuits; a digital-to-analog conversion circuit for converting the signal into an analog signal by the second integration circuit; The configuration includes an addition circuit that adds the outputs of the second integration circuit.

Operation The present invention uses the above-described configuration to generate the signal d at a period T from a certain reference time t=0. + d1+ d2 + “””
+d2N-1 2N signals are stored in the digital memory, and the first holding circuit stores the signals d0, d1*d2 +...
....

N signals of dN-1 are read out from the digital memory and held, and the second holding circuit reads the signal dN r dN+I *dN+2 with a period of 2T at a time of NT≦t and 3NT.
・°°・” + d2N-1 N signals are read out from the digital memory and held, and the output signal of the first holding circuit is used in the first multiplier circuit to calculate L( for 0≦t≦NTK).
t) wo, W2(t-N'J") for NT≦t≦2NT
The output signal of the second holding circuit is multiplied by the second multiplier circuit, and W2 (t)t for 0≦t<NT.
For -1NT≦t<2NTK, w1(t-NT) is carried, and the above-mentioned writing, reading, and amplitude control are repeated at a cycle of 2NT, thereby restoring the pitch.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a pitch restoring device according to an embodiment of the present invention.

21 is a 1-bit analog-to-digital conversion circuit that converts the input signal into a 1-bit digital signal using the gate of the modulation clock generation circuit 10 and outputs it to the digital memory (RAM) 2 that stores this digital signal; 3 is a write address generation circuit; The circuit 11 and the first. a write/read control circuit 4 which uses the address data generated by the second read address generation circuit 12 and 13 as input data to designate a write/read address in the digital memory 2 and generates a write/read control signal; .6 is the first. Second
The first . Second
The holding circuit 6.7 is a monotonically increasing weighting function W1(x) (0<, x≦NT, o2t+ (X)≦1)
Or a monotonically decreasing weight function W2(x), (o<,
xfN T , O<W2(x)<1). Second multiplier circuit % 8 is an adder circuit that adds the output signals of the first and second integrating circuits 16 and 17; An amplitude control circuit that controls the second multiplier circuits 6 and 7,
Signals dO, dl, with period T from a certain reference time t=O,
2N signals of d2, −−, d2N−+ are stored in the digital memory 2, and the first holding circuit 4 holds oft<
Signal d with period 2T at time 2NT. , di , d2 ,
""", dN-+ are read out from the digital memory 2 and held in the second holding circuit 5.
The signal aN, (IN+
+, dN+2.

. . . + d2N-1 N signals are read out from the digital memory 2 and held, and the first holding circuit 4
The first multiplication circuit 6 applies L(t) to the output signal of OSt≦NT, and W2(t-NT) to the output signal of NT<t≦2NT.
The output signal of the second holding circuit 6 is multiplied by W2(t) for 0≦t≦NT and W1(t-NT) for NT≦tq2NT in the second multiplication circuit 7. Match.

The first and second multiplier circuits 6.7 thus obtained
The output signal of the first. The outputs of the first and second integrating circuits 16 and 17 are respectively output as analog outputs through the second integrating circuits 16 and 17, and the outputs of the first and second integrating circuits 16 and 17 are output to the adder circuit 8. 26.2
Reference numeral 7 constitutes a 1-bit digital-to-analog conversion circuit that converts the digital signal from the digital memory into an analog signal as described above.

In each figure, the same parts are given the same numbers.

Here, the principle of the present invention will be explained using FIG. 2.

FIG. 2 shows a principle diagram of the present invention. During double speed playback, time 0≦t (d during 2NT.

2N signals of dl, . . . , d2N-1 are input and written into the digital memory 2. At this time, due to the address given by the first read address generation circuit 12, the first holding circuit 4 has O<t (s
The signals of dO* d1*..., aN-+ are read out, and the addresses given by the second read address generation circuit 13 generate dN and dN++, which were previously missing.
.

......The signal of '12N-1 is read out to the second holding circuit 6 during time NT2t (3NT). Since the two signals obtained by Then, as shown in FIG. 2 (0), the amplitude control T1 causes a discontinuous point to be applied to the signal read out to the second holding circuit 5, as shown in FIG. 2 (g). Amplitude modulation is applied linearly in synchronization with the period of .The method of applying this amplitude modulation is described below.In other words, the amplitude control circuit 9 applies the amplitude modulation to the outputs of the first holding circuit and the second holding circuit. Amplitude control T1 and T2 are performed by changing the multiplication coefficients of the multiplication circuit 6 and the second multiplication circuit 7 from 0 to 1.The two read signals described above are By outputting the sum added by the adding circuit 8 via the integrating circuits 16 and 17, a pitch-restored sound with less missing information and less noise at connection points can be obtained.

The operation of the pitch restoring device configured as above will be explained below.

The 1-bit analog-to-digital conversion circuit 21 converts the input signal into a 1-bit digital signal.

This output digital signal is written into the digital memory 2 every cycle T by the write/read control circuit 3 at the timing shown in FIG. 2 (&).

The addresses written to and read from the digital memory 2 are reset after a certain period of time, as shown in the example of FIG. 2(b). The write address, the first read address, and the second read address are the write address generation circuit 11, the first read address generation circuit 12, and the second read address, respectively.
The data is generated by the read address generation circuit 13 and provided to the digital memory 2 by the write/read control circuit 3 at the timing shown in FIG. 2(a). First holding circuit 4
The second holding circuit 5 holds the signal read out at time D2 in FIG. 2(a) for 2T time, and the second holding circuit 5 holds the signal read out at time D2 in FIG. The first multiplier circuit 6 changes the amplitude of the amplitude shown in FIG. Similarly, the amplitude control T shown in FIG. 2(g)
It is multiplied by 2. The adder circuit 8 adds the output of the first multiplier circuit 6 and the output of the second multiplier circuit 7, passes through the low-pass filter 15, and generates an output signal. Incidentally, FIG. 3 is a timing chart showing the operating state of each part and the arrangement of addresses in this embodiment.

As described above, according to this embodiment, reading is performed twice in one unit time as shown in FIG. 2, signals stored at different times are read out, and the amplitude is controlled and added. It is possible to reduce the loss of information in the pitch-restored voice and to reduce the noise at the connection point.

In this example, 1.2. The following describes a case where an adaptive delta modulator/demodulator is used for the analog/digital converter.

FIG. 4 is a block diagram of its configuration.

In FIG. 4, block (a) shows an adaptive delta modulator. In FIG. 4, %30 is a comparator, 31 is a sampling circuit that outputs a digital signal of 1 pint for each sampling cross-shift, 32 is a step width adaptive logic circuit having an algorithm for determining the quantization step width, and 33 is an up/down counter that outputs an m-bit counter according to the input signal. 34 is a decoder that converts the m-bit signal to n-bit soto; 35 is a pulse width modulation circuit that outputs a pulse width in response to the n-bit soto output signal from the decoder 34; and 36 is a pulse width modulation circuit that outputs a pulse width corresponding to the n-bit soto output signal from the decoder 34; Polarity switching circuit that switches between positive and negative in response to '1' and 'O' outputs, 37
is an integrator circuit that integrates the output from the polarity switching circuit 36 and converts it into an analog signal. Similarly, block (b) shows an adaptive delta demodulator.

In the figures, the same parts are given the same numbers. Therefore, the output of the integrating circuit 37 is passed through a low-pass filter 38 to obtain an analog output.

The operating principle of the present invention will be explained with reference to FIG. The step width adaptation logic circuit 32 sends a signal to the up/down counter 33, which activates the amplifier counter when the step width is to be made larger than the current value, and the down counter when the step width is to be made smaller than the current value. The output of the up-down counter 33 is m = 3 bits, the output of the decoder 34 is n = 4 bits, and the output of the O up-down counter 33 explained in the case of l- is 8 ways (
ooo, ool, -, -, , -, 111). The decoder 34 is not required when output signals of pulse widths are made to correspond in a straight line to eight types of signals. However, linear correspondence alone is not sufficient to reduce noise when there is no signal and to reduce overload noise that occurs at high frequencies or large inputs. Therefore, the decoder 34 makes a non-linear correspondence. The counter output of the 3-bi-soto is non-linear among the 4-bi-7) (2'=16 ways) and is made to correspond, for example, as shown in the table below.

(Hereinafter referred to as gold and white) Expressed in decimal notation: 0.1.2, 3, 5, 7° 11.1
It is 5. Next, pulse width modulation for converting the output of the decoder 34 into a pulse width can be concretely realized by a counter. In this case, a 4-bit counter is used, but the pulse width corresponding to the number of counters determined by the master clock is determined.

For example, Master Kuro, Tsuku MCK = 4.00M
H2 (6M = 0.2 s μsec), the sampling rate of the modulator/demodulator is 2soKH2 (△T==4 μs
ec ), the maximum within one cycle is ΔT/ΔM: 16 (number of counts). At this time, all within one cycle (4 μsec)
1", and the pulse width is also the maximum. Similarly, 12 counts -3μ5ec 8 counts -42μ560 6 counts -1,5μ5ec 4 counts -1μ5ec 3 counts -〇, 76μ5ec 2 counts -) 0.5 μ815c1 count - 1-0 Each pulse width is .25μsec.This pulse width can be located at any position within one town per round, for example, as shown in Fig. 6(b).
, the pulse output width as shown in FIG. 7(1)) can be considered.

A pulse output as described above is obtained every cycle, this signal is switched between positive and negative by the polarity switching circuit 36, and is integrated by the integrating circuit 37 to output an analog signal. In order to further reduce quantization noise and overload noise, it is preferable to increase the number of bits in the up/down counter 33 and the number of pits in the counter 34.

Next, the multiplication method will be explained.

Specifically, the amplitude control circuit 9 generates a signal having a pulse width as shown in FIG. 6(a) and FIG. 7(tortoise) (same), and as shown in FIG. 2(fl) and (g). Like time 0~NT
Varies between. Now, if we assume that the output of the pulse width modulation circuit 35 is P7 in FIG. 6(b) and the output of the amplitude control circuit 9 is D2, P7XD2 becomes zero, which is the original target of P7. I can't use the signal. A similar phenomenon may occur with multiplication under other conditions. Therefore, in this embodiment, the pulse width modulation circuit 36
As shown in FIG. 7(b), temporally dispersed pulses are generated from the output of , and multiplication is performed as described above. Then, in P7XD2, only the first peak becomes "1" and remains, the other three peaks become "0", and a simple output waveform is obtained. Note that multiplication of digital waveforms can be realized by an AND gate circuit.

In this embodiment, amplitude control is performed on the digital signal, but it may be performed after digital-to-analog conversion and then added.

As described above, this embodiment uses an adaptive delta modulator/demodulator in the analog-to-digital conversion system, so the circuit scale is small, and since many parts that can be realized with gate circuits are used, the pitch restoration device can be produced at low cost. can be configured.

Effects of the Invention The present invention includes a second reading number generation circuit, a second holding circuit, and a first . By providing the second multiplier circuit, the adder circuit, and the amplitude control circuit, it is possible to restore the pitch using a signal that has not been used at all in the past.

Therefore, it is possible to realize an excellent pitch restoring device that has less information missing even after pitch restoration, and that can reduce noise at connection points by controlling the amplitude.

Furthermore, if the ADM method is used as the analog-to-digital conversion method, a pitch restoring device can be realized with a small circuit scale and at low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a pitch restoring device according to an embodiment of the present invention, FIG. 2 is a diagram showing the principle of pitch reconstruction according to the present invention, and FIG. 3 is an operational state of a digital memory according to an embodiment of the present invention. FIG. 4 is a configuration block diagram of the analog-to-digital conversion circuit of the present invention, FIG. 5 is a block diagram for explaining the main operations of the analog-to-digital conversion circuit of the present invention, and FIG. 6 is a timing chart showing the address arrangement. 7 is a waveform diagram for explaining the operation of the multiplication circuit of the present invention, and FIG. 8 is a professional pitch restoration device in the conventional example.
Figure 9 shows the original principle after the interval in the conventional example. 2...Digital memory, 3...Write/read control circuit, 4...First holding circuit, 6...Second holding circuit, 6. ...First
multiplication circuit, 7... second multiplication circuit, 8...
...addition circuit, 9...amplitude control circuit, 1Q
...Modulation black, scratch generation circuit, 110. . ...Write address generation circuit, 12...First read address generation circuit, 13...Second read address generation circuit, 1421900. Demodulation clock generation circuit, 16...Low pass filter, 16...
・First integrating circuit, 17... Second integrating circuit,
21...1-bit analog-to-digital conversion circuit, 26.27...1-bit digital to analog conversion circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure θ N complete 2N7 3NT
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ζ To Naki Q to Ra Ra Ra Q
ra C>C>phrase to 鵠 h! Ichigo
~ -ζ Q, CL (:<cs-c<
CL %u - ~ Deaf 1,
l Shizu I+ Naki Q Q Cs
QI Q Q Cs Q Q
Ward

Claims (5)

[Claims] (1) An analog-to-digital conversion circuit that converts an analog input signal into a 1-bit digital signal and outputs it to a digital memory that stores the digital signal, a write address generation circuit, and a first and second read address generation circuit. A write/read control circuit that uses the address data generated in the input data as input data to designate write/read addresses of the digital memory and generates write/read control signals; first and second holding circuits that latch each signal read from the memory at a period of 2T;
For each signal latched in the holding circuit of
1(x)≦1) or a monotonically decreasing weight function W_2(x
) (O≦x≦NT, O≦W_2(x)≦1), and the digital output signals of the first and second multiplication circuits are integrated by the first and second integration. It is equipped with a 1-bit digital-to-analog conversion circuit for converting into an analog signal in a circuit and an addition circuit for adding the outputs of the first and second integration circuits, and converts the signal from a certain reference time to t=O with a period T. d_0, d_1, d_2, ......, d_2_
N_-_1 2N signals are stored in the digital memory, and the first holding circuit stores signals d_0, d_1, d_2, ...
N signals of d_N_-_1 are read out from the digital memory and held, and the second holding circuit satisfies the condition that NT≦t<
Signals d_N, d_N_+_1 with period 2T at time 3NT
, d_N_+_2, ......, d_2_N_-_1
N signals are read from the digital memory and held, and a first multiplier circuit applies W_1(t) to the output signal of the first holding circuit for O≦t≦NT, and NT≦t≦
2NT is multiplied by W_2(t-NT), and the output signal of the second holding circuit is multiplied by the second multiplication circuit, so that O≦
It has an amplitude control circuit that multiplies W_2(t) for t≦NT and W_1(t-NT) for NT≦t≦2NT, and repeats the above writing, reading, and amplitude control at a cycle of 2NT. A pitch restoration device that restores pitch by (2) An adaptive delta modulation method is used for 1-bit analog-to-digital conversion, and the quantization step width is increased when multiple delta-modulated 1-bit digital data "1" or "O" are consecutive. 2. The pitch restoring device according to claim 1, wherein the adaptive quantization step width is determined using a pulse width modulation circuit in a delta modulator having a compression/expansion circuit for varying an integrator output. (3) The pitch restoring device according to claim 2, wherein a linear pulse width modulation circuit is used as the pulse width modulation circuit, which linearly converts the pulse width into a pulse width in accordance with the number of pulses. (4) The pitch restoring device according to claim 2, wherein a non-linear pulse width modulation circuit that non-linearly converts the pulse width into a pulse width corresponding to the number of pulses is used as the pulse width modulation circuit. (5) The pitch restoring device according to claim 1, wherein in the first and second multiplier circuits, both the multiplier and multiplicand signals are pulse width modulated signals.