JPH0519720B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pitch restoring device that restores the pitch of a sound to the same pitch as when it was recorded when an audio signal is played back at twice the recording speed.

BACKGROUND ART In recent years, it has become important to reproduce audio signals at a speed different from the recording speed. If you play back at twice the recording speed, it will take half the time it would normally take, and you can understand the content recorded on a tape recorder or VTR in half the time. However, simply increasing the playback speed to 2
If the pitch is doubled, the pitch will be higher and it will be difficult to hear, and at the same time, the characteristics of the speaker will not be revealed.
Therefore, there is a need for a device that can quickly listen to recorded content in a short time without changing the pitch of the sound.

(For example, "Tape recorder that compresses and expands the time axis of conversation" Nikkei Electronics 1976.7.26) A conventional pitch restoring device will be explained below with reference to the drawings.

FIG. 5 shows a configuration diagram of a conventional pitch restoring device. In FIG. 5, 1 is an analog-to-digital conversion circuit that converts an input signal into a digital signal, 2 is a digital memory that stores the digital signal, and 3 is a write/read control circuit that controls writing to and reading from the digital memory 2. , 4 is a holding circuit that holds the signal read out from the digital memory 2, 16 is a digital-to-analog conversion circuit that converts the digital signal output from the holding circuit 4 into an analog signal, and 10 is for operating the analog-to-digital conversion circuit 1. 11 is a write address generation circuit that supplies the address to be written in the digital memory 2 to the write/read control circuit 3; 12 is a read address generator that supplies the address to be read from the digital memory 2 to the write/read control circuit 3. circuit, 14
1 is a demodulation clock generation circuit that operates the digital-to-analog conversion circuit 16, and 15 is a low-pass filter.

The operation of the pitch restoring device configured as described above will be described below. Fig. 6 shows the principle diagram. When reproducing at the same speed as recording, at time 0t<2NT, d ₀ , d ₁ ,... with a period of 2T.
..., dN _-1 are assumed to be reproduced. At this time, in double speed playback, when 0t<2NT,
Signals d ₀ , d ₁ , ..., d _2N-1 are reproduced. In order to lower the pitch and make it the same pitch as when it was recorded, as shown in Figure 6d, when 0t<2NT, play back d ₀ , d ₁ , ..., d _N-1 with a period of 2T. ,
d _N , d _N+1 , ..., d _2N-1 signals are not regenerated, 2NT
Regenerate d _2N , d _2N+1 , ..., d _3N-1 when t<4NT. The following will be played in the same manner.

This restores the reproduced signal to its original pitch at the time of recording.

Problems to be Solved by the Invention However, in the above method, the signal becomes discontinuous between d _N-1 and d _2N , and noise is generated. Also,
The signals of d _N , d _N+1 , ..., d _2N-1 are not reproduced at all,
There was a problem in that the information of this part of the signal was lost. Also, in order to avoid missing continuous long-range signals, if N is made small,
The number of connection points per time increases and the noise increases.

In view of the above-mentioned problems, the present invention provides a pitch restoring device that uses all input signals and processes discontinuous points, thereby reducing missing information and reducing noise at connection points. be.

Means for Solving the Problems To achieve this object, the pitch restoration device of the present invention comprises an analog-to-digital conversion circuit that samples an input signal at a period T that satisfies the sampling theorem and converts it into a digital signal; a digital memory that stores the digital signals; and output signals d ₀ , d ₁ , d ₂ , ..., d of the analog-to-digital conversion circuit at intervals of period T from a certain reference time t=0 to time t≦2NT. 2N signals of _2N-1 are stored in the digital memory, and the signals d ₀ ,
d ₁ , d ₂ , ..., d _N-1 N signals (sequence 1) are set to 0
The signals d _N , d _N+1 , d _N+2 ,
..., d _2N-1 N signals (sequence 2) with NT≦t≦
a write/read control circuit that reads from the digital memory at intervals of 2T in a time of 3NT and repeatedly controls these digital memories at a cycle of 2NT; and a write/read control circuit that reads from the digital memory under the control of the write/read control circuit. For each signal of series 1, a weighting function W ₁ (t) that monotonically increases with respect to data read out at a time of 0≦t≦NT,
The weight expressed by the weighting function W ₂ (t-NT) that monotonically decreases for the data read out during the time NT≦t≦2NT is set to 0≦ for each signal of series 2.
The weight expressed by the weight function W ₂ (t) for the data read at the time t≦NT, and the weight expressed by the weight function W ₁ (t-NT) for the data read at the time NT≦t≦2NT. an amplitude control circuit that generates a weighting function to apply to the signal and repeats this at a cycle of 2NT; a first circuit that multiplies the weighting function given by the amplitude control circuit and the signal read from the digital memory; A second multiplier circuit, an adder circuit that adds the output signals of the first and second multiplier circuits, and a digital-to-analog conversion circuit that converts the output signal of the adder circuit into an analog signal; It is configured to convert the pitch of the input signal by half using all the samples.

Effect The present invention has the above-described configuration, and the signals d ₀ , d ₁ , d ₂ , ..., with a period T from a certain reference time t=0.
The 2N signals of d _2N-1 are stored in the digital memory, and the first holding circuit stores the signals d ₀ , d ₁ , d ₂ , ..., d _N-1 with a period of 2T at a time of 0t<2NT. N signals are read from the digital memory and held, and the second holding circuit reads the signals d _N , d _N+1 , d _N+2 , ..., d _2N-1 with a period of 2T at a time of NTt<3NT. N signals are read out from the digital memory and latched, and the output signal of the first holding circuit is
In the multiplication circuit, W ₁ (t) for 0t<NT, NT
t2NT is multiplied by W ₂ (t-NT), and the output signal of the second holding circuit is multiplied by W ₂ (t) for 0tNT, and NTt
The pitch is restored by multiplying 2NT by W ₁ (t-NT) and repeating the above writing, reading, and amplitude control at a cycle of 2NT.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a pitch restoring device according to an embodiment of the present invention.

1 is a digital memory (RAM) 2 which samples an input signal with a period T satisfying the sampling theorem using the clock of the modulation clock generating circuit 10, converts it into a digital signal, and stores this digital signal.
An analog-to-digital conversion circuit 3 outputs data to the digital memory 2 using address data generated by the write address generation circuit 11 and the first and second read address generation circuits 12 and 13 as input data.
4 and 5 are write and read control circuits that designate write and read addresses and generate write and read control signals; 1st and 2nd latches at a cycle of 2T
holding circuits, 6 and 7 are first and second holding circuits 4,
For _each signal _latched at
1) or a monotonically decreasing weight function W ₂ (x), (0x
The first multiplication of NT, 0W ₂ (x)1),
a second multiplication circuit; 8 is a first and second multiplication circuit 6;
7 is an addition circuit that adds the output signals; 9 is an amplitude control circuit that controls the first and second multiplication circuits 6 and 7;
The signals d ₀ , d ₁ ,
2N signals of d ₂ , ... d _2N-1 are stored in the digital memory 2, and the first holding circuit 4 holds 0t<
Signals d ₀ , d ₁ , d ₂ , ..., with period 2T in time 2NT
N signals of dN _-1 are read out from the digital memory 2 and held, and the second holding circuit 5 reads out N signals of NTt
Signals d _N , d _N+1 , d _N+2 , with period 2T at time <3NT
..., d _2N-1 N signals are stored in digital memory 2
The first holding circuit 4
The first multiplication circuit 6 outputs the output signal of 0tNT.
W ₁ (t) for NTt2NT, W ₂ (t-
NT) respectively, and the second holding circuit 5
The second multiplier circuit 7 applies the output signal to 0tNT.
W ₂ (t) for NTt2NT, W ₁ (t-
NT). 16 is a digital-to-analog conversion circuit for converting the output signal of the adder circuit 8 into an analog signal. In each figure, the same parts are given the same numbers.

Here, the principle of the present invention will be explained using FIG. 3.

FIG. 3 shows a diagram of the principle of the present invention. During double speed playback, d ₀ , d ₁ ,
..., d _2N-1 2N signals are input and written into the digital memory 2. At this time, depending on the address given by the first read address generation circuit 12, the first holding circuit 4 has the following information between 0t<2NT.
The signals d ₀ , d ₁ , . . . , d _N-1 are read out, and the addresses given by the second read address generation circuit 13 are used to generate the signals d _N , d _N+1 , . . . that were previously missing. , d _2N-1 are read out to the second holding circuit 5 during time NTt<3NT. Since the two signals read out to the first holding circuit 4 and the second holding circuit 5 have a discontinuous point, amplitude control T ₁ , T is performed to eliminate the influence of the discontinuous point on each signal. Add ₂ . 1st
The signal read out to the second holding circuit 4 is controlled by amplitude control _T1 as shown in FIG. 3f, and the signal read out to the second holding circuit 5 is controlled as shown in FIG. 3g. As shown, amplitude modulation is applied linearly in synchronization with the period of the discontinuous point using amplitude control _T2 . A method for adding this amplitude modulation will be described below. That is, the first
The amplitude control T ₁ , perform _T2 . Alternatively, the amplitude controls T 1 and T ₂ may be performed by controlling the first and second ₁ -bit adaptive digital-to-analog conversion circuits 16 by the amplitude control circuit 9. The two read signals described above are added to the adder circuit 8.
By outputting the sum of the summed values, a pitch-restored sound with less missing information and less noise at connection points can be obtained.

The operation of the pitch restoring device configured as above will be explained below.

The analog-to-digital conversion circuit 1 samples the input signal at a period T that satisfies the sampling theorem and converts it into a digital signal. This output digital signal is sent to the write/read control circuit 3.
The data is written to the digital memory 2 (hereinafter referred to as RAM) every period T at the timing shown in FIG. The addresses written to and read from the digital memory 2 are reset after a certain period of time, as shown in an example in FIG. 4b. The write address, the first read address, and the second read address are generated by a write address generation circuit 11, a first read address generation circuit 12, and a second read address generation circuit 13, respectively, and write/read control is performed. The circuit 3 supplies the signal to the digital memory 2 at the timing shown in FIG. 4a. The first holding circuit 4 holds the signal read out at the time of readout _D1 in FIG.
The second holding circuit 5 reads D ₂
The signal read at time is held for 2T time.
The first multiplier circuit 6 converts the amplitude shown in FIG.
The amplitude is changed by changing the multiplication coefficient by the amplitude control circuit 9 and multiplying it by the holding circuit 4. The second multiplier circuit 7 similarly applies the amplitude control _T2 shown in FIG. 3g. The adder circuit 8 adds the output of the first multiplier circuit 6 and the output of the second multiplier circuit 7, passes through the digital-to-analog converter 16 and the low-pass filter 15, returns the signal to an analog signal, and outputs the signal. . Incidentally, FIG. 4 is a timing chart showing the operation of each part in this embodiment.

As described above, according to this embodiment, reading is performed twice in one unit time as shown in FIG. It is possible to reduce the loss of information in the pitch-restored voice and to reduce the noise at the connection point.

In this embodiment, amplitude control is performed on the digital signal, but it may be performed after digital-to-analog conversion and then added.

Next, other embodiments will be described with reference to the drawings. FIG. 2 shows the configuration of a second embodiment of the present invention.

In this embodiment, the same components as in the first embodiment are given the same numbers. This embodiment differs from the configuration shown in FIG. 1 because it uses an adaptive delta modulation method for analog-to-digital conversion. In FIG. 2, 21 is a 1-bit adaptive analog-to-digital conversion circuit, 26 and 27 are 1-bit adaptive digital-to-analog conversion circuits, 28 is an addition circuit for analog signals, and 29 is a 1-bit adaptive digital-to-analog conversion circuit. This is an amplitude control circuit for changing the amplitude by controlling the quantization widths of 26 and 27. For a method of changing the amplitude using the adaptive delta modulation method, Japanese Patent Application No. 59-245141 can be cited as a reference.

As described above, in this embodiment, since the adaptive delta modulation method is used as the analog-to-digital conversion method, the pitch restoring device can be configured with a small circuit scale and at low cost.

Effects of the Invention As described above, according to the present invention, not only can discontinuities at waveform connection points be improved, but also the loss of information contained in an input signal can be reduced compared to the conventional method. Since this method uses all input signal samples to obtain pitch-restored audio, conventional devices that only partially expand the time axis of the input signal may completely discard the audio signal. The characteristic parts of the consonants can also be restored satisfactorily.

In other words, the clarity of the pitch-restored voice is improved compared to the conventional example, and not only is the naturalness improved by reproducing smooth waveform connections, but also the intelligibility of the reproduced sound can be improved, resulting in high-quality reproduction. This makes it possible to realize an excellent pitch restoration device that can obtain sound.

Furthermore, if an adaptive delta modulation method is used as the analog-to-digital conversion method, a pitch restoring device can be realized with a small circuit scale and at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a pitch restoring device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the construction of a pitch restoring device according to another embodiment, and FIG. 3 is a block diagram showing the construction of a pitch restoring device according to another embodiment of the present invention. 4 is a timing chart showing the operation of the digital memory in an embodiment of the present invention, FIG. 5 is a block diagram of a conventional pitch restoration device, and FIG. 6 is a diagram of the principle of pitch restoration in a conventional example. It is. 1...Analog-digital conversion circuit, 2...
Digital memory, 3...Write/read control circuit, 4...First holding circuit, 5...Second holding circuit, 6...First multiplication circuit, 7...Second multiplication circuit, 8 ...Addition circuit, 9...Amplitude control circuit, 10...Modulation clock generation circuit, 11...Write address generation circuit, 12...First read address generation circuit, 13...Second read address generation circuit, 14...Demodulation clock generation circuit, 15...Low pass filter, 16...Digital-to-analog conversion circuit.

Claims (1)

[Claims] 1. An analog-to-digital conversion circuit that samples an input signal at a period T that satisfies the sampling theorem and converts it into a digital signal, a digital memory that stores the digital signal, and a certain reference time t=0. 2N output signals d ₀ , d ₁ , _{d 2 ,} . Signal d ₀ ,
N signals (sequence 1) of d ₁ , d ₂ , ..., d _N-1 are read out from the digital memory at intervals of period 2T at a time of 0≦t≦2NT, and the signals d _N , d _{N+ 1} ,
d _N+2 , ..., d _2N-1 N signals (sequence 2) as NT
a write/read control circuit that reads data from the digital memory at intervals of a period of 2T at a time of ≦t≦3NT, and repeatedly controls these digital memories at a period of 2NT; For each signal of series 1 read from , a weighting function W ₁ (t) that monotonically increases for data read at a time of 0≦t≦NT,
For each signal of series 2, the weight expressed by the weighting function W ₂ (t-NT) that monotonically decreases for the data read at a time of NT≦t≦2NT is calculated as follows: A weighting function W ₂ (t) is applied to the data read out at a time, and a weighting function W ₁ (t-NT) is applied to the data read out at a time NT≦t≦2NT. an amplitude control circuit that generates a weighting function for and repeats this at a cycle of 2NT, and first and second amplitude control circuits that multiply the weighting function given by the amplitude control circuit and the signal read from the digital memory. a multiplier circuit; an adder circuit that adds the output signals of the first and second multiplier circuits; and a digital-to-analog converter circuit that converts the output signal of the adder circuit into an analog signal; A pitch restoring device that converts the pitch of an input signal into half by using all of the samples.