JPS61228499A - Musical interval restoring apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pitch restoring device that restores the pitch of a sound to the same pitch as when it was recorded when an audio signal is played back at twice the recording speed.

2. Description of the Related Art In recent years, it has become important to reproduce audio signals at a speed different from the recording speed. If you play back at twice the recording speed,
It takes half the time it would normally take, and allows you to understand the content recorded on a tape recorder or VTR in half the time. but,
If you simply double the playback speed, the pitch will not be high enough.
It becomes difficult to hear, and at the same time, the characteristics of the speaker are not highlighted.

Therefore, there is a need for a device that can quickly listen to recorded content in a short time without changing the pitch of the sound.

(For example, "Cheap Recorder for Compressing and Expanding the Time Axis of Conversation" Nikkei Electronics 1976.7) Below, a conventional pitch restoring device will be explained with reference to the drawings.

FIG. 6 shows a configuration diagram of a conventional pitch restoring device. In FIG. 6, 1 is an analog-to-digital conversion circuit that converts an input signal into a digital signal, 2 is a digital memory that stores the digital signal, and 3 is a write/read control circuit that controls writing and reading from the digital memory 2. , 4 is a holding circuit that holds the signal read out from the digital memory 2, 16 is a digital-analog conversion circuit that converts the digital signal output from the holding circuit 4 into an analog signal, and 10 is a circuit that operates the analog-digital conversion circuit 1. 11 is a write address generation circuit that supplies the address to be written in the digital memory 2 to the write/read control circuit 3; 12 is a read address generator that supplies the address to be read from the digital memory 2 to the write/read control circuit 3. circuit, 14
1 is a demodulation clock generation circuit that operates the digital-to-analog conversion circuit 16, and 16 is a low-pass filter.

The operation of the pitch restoring device configured as described above will be described below. Fig. 6 shows the principle diagram. When reproducing at the same speed as recording, at time 0<:t2NT, d with a period of 2T. , dl,...mark.

Suppose that N signals dN-j are reproduced. At this time,
For double speed playback, O<;:t (at 2NT, dOr
The signals of dl p..., d2N-j are reproduced. In order to lower the pitch and make it the same pitch as when recording, as shown in Figure 6(d), oct<d in 2NT. , dl, ..., dN-1, dN, dN
+1゜..., the signal of d2N-1 is not regenerated, and 2NT minus 4NT is d2N+ d2N+1 +......+
Play d5N-J.

The following will be played in the same manner.

This restores the reproduced signal to its original pitch at the time of recording.

Problems to be Solved by the Invention However, in the above method, the signal is discontinuous between d8-1 and d2N, and noise is generated. Also, dN・6+
1・°゛°°°・42N-1 signal is not reproduced at all,
There was a problem in that the information of this part of the signal was lost. In addition, if N is made small in order to avoid missing signals over a long period of time, the number of connection points per time increases and noise increases.

In view of the above-mentioned problems, the present invention provides a pitch restoring device that uses all input signals and processes discontinuous points, thereby reducing missing information and reducing noise at connection points. be.

Means for Solving the Problems In order to achieve this object, the pitch restoring device of the present invention samples an input signal with a period T that satisfies the sampling theorem, converts it into a digital signal, and stores this digital signal. An analog/digital conversion circuit for outputting to memory, a write address generation circuit, and a first . a write/read control circuit that uses address data generated by the second read address generation circuit as input data to designate a write/read address in the digital memory and generates a write/read control signal; The first . a second holding circuit; a first holding circuit; For each signal latched by the second holding circuit, a monotonically increasing weighting function Wj(X) (0<X<N T #
O<Wl (X)<1 ) or a monotonically decreasing weighting function "2(")* (oku"ku'T+o<"2 (x)
<: 1). a second subtraction circuit; a first subtraction circuit; an amplitude control circuit that controls the second subtraction circuit; an addition circuit that adds the output signals of the second subtraction circuit;
The configuration includes a digital-to-analog conversion circuit for converting the output signal of the adder circuit into an analog signal.

Effect of the present invention With the above-described configuration, the signal dOr dl + d2 + .
+d2N-1 2N signals are stored in the digital memory, and the first holding circuit stores the signal d at a period of 2T at a time of 0<t>2NT. , d4. d2. ..., N of dN-1
The signals of
Signal dN + dN+1 + dll+2 +...
・, d2N-1 N signals are read out from the digital memory and held, and the output signal of the first holding circuit is multiplied by the first subtraction circuit, and W1( t)
, IT<t<2 N T is multiplied by W2(t-NT), and the output signal of the second holding circuit is
In the subtraction circuit, ``2(t) for Q≦t≦IT, NT
Kut<;: Against 2N-cho! 1(t-N'r) and repeating the above writing, reading, and amplitude control at a period of 2NT to restore the pitch.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a pitch restoring device according to an embodiment of the present invention.

1 is an analog/digital circuit that samples an input signal with a period T that satisfies the sampling theorem using the clock of the modulation clock generation circuit 10, converts it into a digital signal, and outputs it to a digital memory IJ (RAM) 2 that stores this digital signal. A conversion circuit 3 is a write address generation circuit 11 and a first
．． The digital memory 2 uses the address data generated by the second read address generation circuits 12 and 13 as input data.
Write and read control circuits 4 and 5 specify write and read addresses of the first . The first . The second holding circuit, 6, 7, is the first holding circuit. For each signal latched by the second holding circuits 4 and 5, a monotonically increasing weighting function W, (x) (o<x<N T ,
O<:W, (X)<1) or a monotonically decreasing weight function "2(x), (0<, x<.

N T , O<W2 (x) <1 ). The second subtraction circuit, 8, is the first subtraction circuit. Second subtraction circuit 6
, 7, an adder circuit 9 adds the output signals of the first . An amplitude control circuit that controls the second subtraction circuits 6 and 7 generates a signal d at a period T from a certain reference time 1=0. , dl, d2゜...
...2N signals of d2N-1 are stored in the digital memory 2.
The signal d is stored in the first holding circuit 4 at a period of 2T at a time of 0≦t<2NT. , d4. d2.・・・・・・、
(N signals of iN-1 are read out from the digital memory 2 and held, and the second holding circuit 5 reads NT<:t(3
Signal dN + dN+1 r with period 2T at time IT
dN+□,・・.

, d2N-1 are read out from the digital memory 2 and held, and a first subtraction circuit 6 adds W1(t ), IT x 2NT is multiplied by W2(t-NT), and the output signal of the second holding circuit 5 is multiplied by the second subtraction circuit 7, and the result is "2" for O<t<NT. (t), N
T <t <2 N T is multiplied by W1 (t-IT), respectively. 16 is a digital-to-analog conversion circuit for converting the output signal of the adder circuit 8 into an analog signal; the same parts are given the same numbers in each figure.

Here, the principle of the present invention will be explained using FIG. 3.

FIG. 3 shows a principle diagram of the present invention. During double speed playback, time o < t (d., dl between 2N TO.

..., d2N-1 2N signals are input and written into the digital memory 2. At this time, according to the address given by the first read address generation circuit 12, the first holding circuit 4 has O<t (dO+d1+
. . . , the signal of d yaw 1 is read out, and the addresses given by the second read address generation circuit 13 are used to generate the signals dN, dll+1 . .......

The signal at d2N-4 is at time NT
The data is read out to the holding circuit 6. The first holding circuit 4 and the second holding circuit 4
Since the two signals read out to the holding circuit 5 have a discontinuous point, amplitude control T, , T2 is applied to each signal so as to eliminate the influence of the discontinuous point. The signal read out to the first holding circuit 4 is controlled by the amplitude control T1 as shown in FIG. As shown in FIG. 3(g), amplitude modulation is applied linearly in synchronization with the period of the discontinuous points by amplitude control T2.

A method for adding this amplitude modulation will be described below. Namely.

The first subtraction circuit 6 and the second subtraction circuit 7 are controlled by the amplitude control circuit 9 with respect to the outputs of the first holding circuit and the second holding circuit.
The amplitude control T, , T2 is performed by changing the multiplication coefficient of from 0 to 1. Alternatively, by controlling the first and second 1-bit adaptive digital-analog conversion circuits 16 by the amplitude control circuit 9, the amplitude control T1. T
You may also do step 2.

By adding the two read signals described above in the adding circuit 8 and outputting the result, a pitch-restored sound with less information loss and less noise at the connection point can be obtained. become.

The operation of the pitch restoring device configured as above will be explained below.

The analog-to-digital conversion circuit 1 samples the input signal at a period T that satisfies the sampling theorem and converts it into a digital signal. This output, a digital signal, can be written,
The read control circuit 3 reads the digital memory 2 (hereinafter referred to as RAM) every period T at the timing shown in FIG. 6 (2L).
will be written to. The addresses written to and read from the digital memory 2 are reset after a certain period of time, as shown in the example of FIG. 6(b). The write address, the first read address, and the second read address are generated by the write address generation circuit 11, the first read address generation circuit 12, and the second read address generation circuit 13, respectively, and are generated by the write/read control circuit 3. So, Figure 6 (2L
) is given to the digital memory 2 at the timing. The first holding circuit 4 holds the signal read out at the time of readout D2 in FIG. do.

The first subtraction circuit 6 changes the multiplication coefficient of the amplitude shown in FIG.
By multiplying by , it brings about a change in amplitude. Second
Similarly, the subtraction circuit 7 multiplies by 2 using the amplitude control shown in FIG. 3(g). The adding circuit 8 adds the output of the first subtracting circuit 6 and the output of the second subtracting circuit 7, returns it to an analog signal through a digital-to-analog converter 16 and a low-pass filter 15, and outputs the signal. shall be. Incidentally, FIG. 4 is a timing chart showing the operation of each part in this embodiment.

As described above, according to this embodiment, reading is performed twice in one unit time as shown in FIG. 6, and signals stored at different times are read out, amplitude controlled, and added. It is possible to reduce the loss of information in the pitch-restored voice and to reduce the noise at the connection point.

In this embodiment, amplitude control is performed on the digital signal, but it may be performed after digital-to-analog conversion and then added.

Next, other embodiments will be described with reference to the drawings.

FIG. 2 shows the configuration of a second embodiment of the present invention.

In this embodiment, the same components as in the first embodiment are given the same numbers. This embodiment differs from the configuration shown in FIG. 1 because it uses the ADM method for analog-to-digital conversion. In FIG. 2, 21 is a 1-bit adaptive analog-to-digital conversion circuit, 26.27 is a 1-bit adaptive digital-to-analog conversion circuit, 28 is an addition circuit for analog signals, and 29 is a 1-bit adaptive analog-to-digital conversion circuit. This is an amplitude control circuit that changes the amplitude by controlling the quantization width of 26.27. As a method of changing the amplitude using the ADM method, the patent application No. 1983-24
/4/ issue etc. can be cited as a reference.

As described above, in this embodiment, since the ADM method is used as the analog-to-digital conversion method, the pitch restoring device can be configured with a small circuit scale and at low cost.

Effects of the Invention The present invention includes a second reading number generation circuit, a second holding circuit, and a first . By providing the second subtraction circuit, addition circuit, and amplitude control circuit, pitch can be restored using signals that have not been used at all in the past.

Therefore, it is possible to realize an excellent pitch restoring device that has less information missing even after pitch restoration, and that also has the effect of reducing noise at connection points by controlling the amplitude.

Furthermore, if the ADM method is used as the analog-to-digital conversion method, a pitch restoring device can be realized with a small circuit scale and at low cost.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a pitch restoring device according to an embodiment of the present invention, Fig. 2 is a block diagram showing the composition of a pitch restoring device according to an embodiment of the present invention, and Fig. 3 is a block diagram showing the composition of a pitch restoring device according to an embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the digital memory in one embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional pitch restoration device, and FIG. 6 is a diagram showing the principle of pitch restoration in the conventional example. 1...Analog-digital conversion circuit, 2...
...Digital memory, 3...Write/read control circuit, 4...First holding circuit, 5...Second holding circuit, 6・・・・・・First
subtraction circuit, 7... Second subtraction circuit, 8...
...Addition circuit, 9...Amplitude control circuit, 1o.
... Modulation clock generation circuit, 11 ... Write address generation circuit, 12 ... First read address generation circuit, 13 ... Second read address generation circuit Circuit, 14... Demodulation clock generation circuit, 15
...Low pass filter, 16...Digital-to-analog conversion circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
figure

Claims (2)

[Claims] (1) An analog-to-digital conversion circuit that samples an input signal at a period T that satisfies the sampling theorem, converts it into a digital signal, and outputs it to a digital memory that stores the digital signal, and a write address generation circuit. 1st, 2nd
a write/read control circuit which uses the address data generated by the read address generation circuit as input data to designate a write/read address in the digital memory and generates a write/read control signal;
first and second latches each signal read from the digital memory at a period of 2T according to the read address of
A weight function W_1(x) that increases monotonically for each signal latched by the holding circuit and the first and second holding circuits.
(0≦x≦NT, 0≦W_1(x)≦1) or monotonically decreasing weight function W_2(x), (0≦x≦NT, 0≦W
_2(x)≦1); first and second multiplier circuits that multiply the output signals of the first and second subtraction circuits; and an addition circuit that adds the output signals of the first and second subtraction circuits; and converts the output signal of the addition circuit into an analog signal. It is equipped with a digital-to-analog conversion circuit for converting signals d_0, d_1, d_2 at a period T from a certain reference time t=0.
, ..., d_2_N_-_1 are stored in the digital memory, and in the first holding circuit, 0≦t
Signals d_0, d_1, d_ with a period of 2T at a time of <2NT
2, ..., d_N_-_1 are read out from the digital memory and held, and the second holding circuit reads out the signals d_N, d with a period of 2T at a time of NT≦t<3NT.
_N_+_1, d_N_+_2, ..., d_2_N_
-_1 are read from the digital memory and held, and a first multiplier circuit converts the output signal of the first holding circuit into W_1(t) for 0≦t≦NT.
≦T≦2NT is multiplied by W_2(t-NT), and the output signal of the second holding circuit is multiplied by W_2(t) for 0≦t≦NT and NT≦t≦ 2N
It has an amplitude control circuit that multiplies T by W_1 (t-NT), and performs the above writing, reading,
A pitch restoring device that restores pitch by repeating amplitude control at a cycle of 2NT. (2) Use adaptive delta modulation method for analog-to-digital conversion, and use 1-bit adaptive digital modulation method for amplitude control.
2. The pitch restoration device according to claim 1, wherein the pitch restoration device is implemented in an analog conversion circuit.