JPS6210918A - Pulse generating circuit - Google Patents

Pulse generating circuit

Info

Publication number
JPS6210918A
JPS6210918A JP15107385A JP15107385A JPS6210918A JP S6210918 A JPS6210918 A JP S6210918A JP 15107385 A JP15107385 A JP 15107385A JP 15107385 A JP15107385 A JP 15107385A JP S6210918 A JPS6210918 A JP S6210918A
Authority
JP
Japan
Prior art keywords
input
inverters
fet
fets
active load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15107385A
Other languages
Japanese (ja)
Other versions
JPH0666658B2 (en
Inventor
Akio Shimano
嶋野 彰夫
▲高▼木 弘光
Hiromitsu Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15107385A priority Critical patent/JPH0666658B2/en
Publication of JPS6210918A publication Critical patent/JPS6210918A/en
Publication of JPH0666658B2 publication Critical patent/JPH0666658B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To attain start of pulse oscillation only with application of a power supply even when variation exists in characteristics between FETs by providing an active load field effect transistor (FETs) and the 1st resistor connected in parallel. CONSTITUTION:A couple of inverters comprising the active load FETs 13, 14 connected in parallel and a FET using the 1st resistors 19, 20 as loads a couple of capacitors 15, 16 connecting mutulaly input and output terminals of the inverters, and the 2nd resistors 17, 18 connected between the input terminal of each inverter and a constant potential are provided. Since the current saturation characteristic of the load of the inverters slows down by the 1st resistors 19, 20, the input input voltage range having >=1 voltage gain is widened. Thus, even when variation exists in the characteristic of each FET, positive feedback is applied by the application of power supply only and the pulse oscillation is started automatically.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ディジタル信号処理などに用いることができ
るパルス発生回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse generation circuit that can be used for digital signal processing and the like.

従来の技術 近年、パルス発生口路は、ディジタル信号処理系におい
て、クロック信号発生などに使われており、MO8形集
積回路に内蔵されることから、電界効果トランジスタ(
以下rFETJと称す)を用いたものが!1要となって
いる。
2. Description of the Related Art In recent years, pulse generation circuits have been used for clock signal generation in digital signal processing systems, and since they are built into MO8 type integrated circuits, field effect transistors (
Hereinafter referred to as rFETJ) is used! 1 is required.

以下、このような従来のパルス発生回路について第4図
を用いて説明する。第4図は従来のパルス発生回路であ
る無安定マルチバイブレータの回路図で、、2は負のし
きい電圧を有するNチャンネルのスイッチングFETで
あり、交互にスイッチングを繰り返す。3.4はそれぞ
れスイッチングFET、2の負荷となる能動負荷トラン
ジスタで、FETから構成されている。5,6は容量、
7,8は抵抗であり、遅延回路を形成し、無安定マルチ
バイブレータの発振周波数を決定するものである。
Hereinafter, such a conventional pulse generating circuit will be explained using FIG. 4. FIG. 4 is a circuit diagram of an astable multivibrator which is a conventional pulse generating circuit, and 2 is an N-channel switching FET having a negative threshold voltage, which repeats switching alternately. 3.4 is a switching FET, and 2 is an active load transistor serving as a load, which is composed of FETs. 5 and 6 are capacities,
7 and 8 are resistors that form a delay circuit and determine the oscillation frequency of the astable multivibrator.

次に動作を説明する。まずスイッチングFET1と能動
負荷トランジスタ3、およびスイッチングFET2と能
動負荷トランジスタ4とは、共にインバータを形成して
おり、スイッチングFET、2のゲート端子を入力、ド
レイン端子を出力とみると、相互の入出力が容量5,6
を通して接続されている。この2つのインバータは電圧
利得を有しているので、何らかの雑音が発生すると、=
  2  − その雑音が増幅され、正帰還がかかるため、容量5,6
と抵抗7,8との時定数で決まるパルス発振を生じる。
Next, the operation will be explained. First, the switching FET 1 and the active load transistor 3, and the switching FET 2 and the active load transistor 4 together form an inverter.If we consider the gate terminal of the switching FET 2 as the input and the drain terminal as the output, we can see that the switching FET 1 and the active load transistor 3 have mutual input/output. is capacity 5,6
connected through. These two inverters have voltage gain, so if some noise occurs, =
2 - The noise is amplified and positive feedback is applied, so the capacitance 5,6
A pulse oscillation is generated which is determined by the time constant of the resistors 7 and 8.

従って、電源を投入しただけでパルス発振を開始するた
めには、スイッチングFET、2のゲート電位が零のと
き、2つのインバータの電圧利得が1以上である必要が
ある。
Therefore, in order to start pulse oscillation just by turning on the power, it is necessary that the voltage gains of the two inverters be 1 or more when the gate potential of the switching FET 2 is zero.

発明が解決しようとする問題点 しかしながら、上記従来の構成によれば、電流飽和特性
のよい能動負荷を用いているので、インバータの電圧利
得が1以上となるゲート電位の範囲が極めて狭く、この
ためFET間の特性にバラツキがある場合、ゲート電位
が零の時の電圧利得が1以下となって電源を投入するだ
けではパルス発振が開始されないとという欠点を有して
いた。
Problems to be Solved by the Invention However, according to the above conventional configuration, since an active load with good current saturation characteristics is used, the range of gate potentials in which the voltage gain of the inverter is 1 or more is extremely narrow. If there are variations in characteristics between FETs, the voltage gain when the gate potential is zero becomes 1 or less, and pulse oscillation cannot be started simply by turning on the power.

本発明は上記従来の欠点を解消するもので、FET間の
特性にバラツキがある場合でも、電源の投入だけでパル
ス発振を開始さ往ることのできるパルス発生回路を提供
することを目的とする。
The present invention solves the above-mentioned conventional drawbacks, and aims to provide a pulse generation circuit that can start pulse oscillation simply by turning on the power even if there are variations in characteristics between FETs. .

問題点を解決するための手段 上記問題点を解決するため、本発明のパルス発主回路は
、互いに並列に接続された能動負荷電界効果トランジス
タと第1の抵抗とを負荷とする電界効果トランジスタか
らなる一対のインバータと、これらインバータの入力端
子と出力端子とを互いに接続する一対の容量と、前記各
インバータの入力端子と定電位との間に接続された第2
の抵抗とを備えた構成としたものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the pulse generation circuit of the present invention consists of field effect transistors whose loads are an active load field effect transistor and a first resistor connected in parallel with each other. a pair of inverters, a pair of capacitors connecting the input terminals and output terminals of these inverters to each other, and a second capacitor connected between the input terminal of each inverter and a constant potential.
The structure has a resistance of .

作用 上記構成によれば、インバータの負荷の電流飽和特性が
第1の抵抗により緩やかとなるので、電圧利得が1以上
となる入力電圧範囲を広くとることが出来る。従って各
FETの特性にバラツキがある場合にも、電源の投入だ
けで正帰還がかかり、パルス発振が自動的に開始される
こととなる。
Effects According to the above configuration, the current saturation characteristic of the load of the inverter is made gentle by the first resistor, so that the input voltage range in which the voltage gain is 1 or more can be widened. Therefore, even if there are variations in the characteristics of each FET, positive feedback is applied just by turning on the power, and pulse oscillation is automatically started.

実施例 以下、本発明の一実施例を第1図〜第3図に基づいて説
明する。
EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 3.

第1図は本発明の一実施例におけるパルス発生回路であ
る無安定マルチバイブレータの回路図で、11、12は
負のしきい値を有するNチャンネルのスイツチングFE
T、13.14はFETからなる能動負荷トランジスタ
、15.16は容量、17.18は抵抗で、これらは第
4図に示す従来の構成と同じもので□ある。19.20
は能動負荷トランジスタ13.14と並列接続されて負
荷の電流飽和特性を緩やかにするための抵抗である。
FIG. 1 is a circuit diagram of an astable multivibrator which is a pulse generation circuit in an embodiment of the present invention, and 11 and 12 are N-channel switching FEs having negative thresholds.
T, 13.14 is an active load transistor consisting of an FET, 15.16 is a capacitance, and 17.18 is a resistance, which are the same as the conventional configuration shown in FIG. 19.20
is a resistor connected in parallel with the active load transistors 13 and 14 to moderate the current saturation characteristics of the load.

次に動作を説明する。まず、インバータの入出力特性に
ついて説明するに、第2図はインバータを構成するスイ
ッチングFET1、12と負荷との関係の説明図で、(
A)は従来のFET能動負荷、(B)は抵抗負荷、(C
)は本実施例における負荷曲線をそれぞれ示している。
Next, the operation will be explained. First, to explain the input/output characteristics of the inverter, FIG.
A) is a conventional FET active load, (B) is a resistive load, (C
) respectively show the load curves in this example.

第3図はインバータの入出力特性の説明図で、(D)(
E)(F)は、FET能動負荷、抵抗負荷、本実施例の
場合の入出力特性をそれぞれ示している。FET能動負
荷を用いると、出力電圧の変化が急峻で電圧利得を大き
くとれる反面、第2図よりわかるように、FET特性と
能動負荷電流にばらつきを生じた時、入出力特性が左右
に移動し、入力電圧が零のところでの電圧利得が1以下
となって、電源投入だけでは自己発振を開始しなくなる
。また抵抗負荷では、利得を大きくとれず、抵抗が小さ
過ぎると利得が1以下となり、同様の結果となる。本実
施例では、FET能動負荷の電流飽和を抵抗によって緩
やかにしているので、第3図に(F)で示すように、イ
ンバータの入出力特性は、電圧利得を保ちつつ、入力電
圧の範囲を広くすることができるので、素子のバラツキ
があっても確実に発振を起こすパルス発振回路を構成す
ることができる。
Figure 3 is an explanatory diagram of the input/output characteristics of the inverter, (D) (
E) and (F) respectively show the input/output characteristics of the FET active load, resistive load, and this example. When using a FET active load, the output voltage changes rapidly and a large voltage gain can be achieved, but as shown in Figure 2, when variations occur in the FET characteristics and active load current, the input/output characteristics shift left and right. , the voltage gain becomes less than 1 when the input voltage is zero, and self-oscillation does not start just by turning on the power. Further, with a resistive load, a large gain cannot be obtained, and if the resistance is too small, the gain will be less than 1, resulting in the same result. In this example, the current saturation of the FET active load is made gentle by the resistor, so the input/output characteristics of the inverter are such that the input voltage range can be controlled while maintaining the voltage gain, as shown by (F) in Figure 3. Since it can be made wider, it is possible to construct a pulse oscillation circuit that reliably generates oscillation even if there are variations in elements.

発明の効果 以上述べたごとく本発明によれば、FETにより構成さ
れる無安定マルチバイブレータ回路の負荷として、能動
負荷と並列に抵抗を設けたので、素子のばらつきがあっ
ても確実に電源投入のみで自己発振を開始させることが
できる。
Effects of the Invention As described above, according to the present invention, a resistor is provided in parallel with the active load as the load of the astable multivibrator circuit composed of FETs, so even if there are variations in the elements, the power can be turned on without fail. can start self-oscillation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例におけるパルス発生回路とし
ての無安定マルチバイブレータの回路図、第2図はFE
Tと負荷との関係の説明図、第3図はインバータの入出
力特性の説明図、第4図は従来のパルス発生回路として
の無安定マルチバイブレータの回路図である。 11、12・・・スイッチングFET、 13.14・
・・能動負荷トランジスタ、15.16・・・容量、1
7〜20・・・抵抗代理人   森  本  義  弘 第1図 ti、tz−一一スイッナシグFET t7.歴−@ 177゜ 第2図 ソース・P’Lイ〉M電圧
Figure 1 is a circuit diagram of an astable multivibrator as a pulse generation circuit in one embodiment of the present invention, and Figure 2 is a circuit diagram of an FE.
FIG. 3 is an explanatory diagram of the relationship between T and load, FIG. 3 is an explanatory diagram of the input/output characteristics of an inverter, and FIG. 4 is a circuit diagram of an astable multivibrator as a conventional pulse generating circuit. 11, 12... switching FET, 13.14.
...Active load transistor, 15.16...Capacity, 1
7-20...Resistance agent Yoshihiro Morimoto Figure 1 ti, tz-11 SWINASIG FET t7. History - @ 177゜Figure 2 Source P'L〉M voltage

Claims (1)

【特許請求の範囲】[Claims] 1、互いに並列に接続された能動負荷電界効果トランジ
スタと第1の抵抗とを負荷とする電界効果トランジスタ
からなる一対のインバータと、これらインバータの入力
端子と出力端子とを相互に接続する一対の容量と、前記
各インバータの入力端子と定電位との間に接続された第
2の抵抗とを備えたパルス発生回路。
1. A pair of inverters consisting of a field effect transistor whose load is an active load field effect transistor and a first resistor connected in parallel to each other, and a pair of capacitors that interconnect the input terminal and output terminal of these inverters. and a second resistor connected between the input terminal of each of the inverters and a constant potential.
JP15107385A 1985-07-08 1985-07-08 Pulse generator Expired - Lifetime JPH0666658B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15107385A JPH0666658B2 (en) 1985-07-08 1985-07-08 Pulse generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15107385A JPH0666658B2 (en) 1985-07-08 1985-07-08 Pulse generator

Publications (2)

Publication Number Publication Date
JPS6210918A true JPS6210918A (en) 1987-01-19
JPH0666658B2 JPH0666658B2 (en) 1994-08-24

Family

ID=15510714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15107385A Expired - Lifetime JPH0666658B2 (en) 1985-07-08 1985-07-08 Pulse generator

Country Status (1)

Country Link
JP (1) JPH0666658B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011259192A (en) * 2010-06-09 2011-12-22 Sony Corp Multivibrator circuit and voltage conversion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011259192A (en) * 2010-06-09 2011-12-22 Sony Corp Multivibrator circuit and voltage conversion circuit

Also Published As

Publication number Publication date
JPH0666658B2 (en) 1994-08-24

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