JPS5848515A - Nonlinear amplifying circuit - Google Patents

Nonlinear amplifying circuit

Info

Publication number
JPS5848515A
JPS5848515A JP56148510A JP14851081A JPS5848515A JP S5848515 A JPS5848515 A JP S5848515A JP 56148510 A JP56148510 A JP 56148510A JP 14851081 A JP14851081 A JP 14851081A JP S5848515 A JPS5848515 A JP S5848515A
Authority
JP
Japan
Prior art keywords
transistors
signal
circuit
input
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56148510A
Other languages
Japanese (ja)
Other versions
JPS6362132B2 (en
Inventor
Takashi Kakimoto
隆司 垣本
Fumiaki Araki
荒木 文章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56148510A priority Critical patent/JPS5848515A/en
Publication of JPS5848515A publication Critical patent/JPS5848515A/en
Publication of JPS6362132B2 publication Critical patent/JPS6362132B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G7/00Volume compression or expansion in amplifiers
    • H03G7/002Volume compression or expansion in amplifiers in untuned or low-frequency amplifiers, e.g. audio amplifiers
    • H03G7/005Volume compression or expansion in amplifiers in untuned or low-frequency amplifiers, e.g. audio amplifiers using discontinuously variable devices, e.g. switch-operated

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE:To obtain a small gain for a low input signal and a large gain for high input signal, by controlling the amount of negative feedback with a nonlinear switching element. CONSTITUTION:Transistors(TRs) Q3, Q4 constitute a differential amplifying circuit and TRs Q1, Q2 form a current mirror circuit. A TRQ5 forms an emitter follower circuit. With the absence of input signals, voltages V1, V2 are set to turn off TRs Q6, Q7. When a signal of input level for the AC level of VBQ4 which satisfies V1+VBEQ7>VBO4>V2-VBEQ6 is inputted, the TRs Q6, Q7 turn off. Next, the signal of input level in which the AC level of the VBQ4 satisfies V1+ VBEQ7<VBEQ7 and V2-VBEQ6>VBQ4 is inputted, the TRQ7 turns on and one end of a resistor R3 is grounded as AC. Thus, in this amplifier, a small gain can be obtained for a low input signal and a high gain to a high input signal, respectively.

Description

【発明の詳細な説明】 本発明は、非線型増幅回路に関し、詳しくは、低入力レ
ベルの信号に対しては小なる一利得を有し、高入力レベ
ルの信号に対しては、大なる利得を有する様にした非線
型増幅回路を提供するものであ − る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonlinear amplifier circuit, and more particularly, it has a small gain for low input level signals and a large gain for high input level signals. The present invention provides a nonlinear amplifier circuit having the following characteristics.

第1図は、通常の負帰還増幅回路の基本原理を説明する
ためのブロック図である。この増幅回路における本体の
能動負荷型差動増幅回路の利得をム0負帰還ループにお
ける伝達関数をG(s)とする。
FIG. 1 is a block diagram for explaining the basic principle of a normal negative feedback amplifier circuit. In this amplifier circuit, the gain of the active load type differential amplifier circuit of the main body is Mu0, and the transfer function in the negative feedback loop is G(s).

入力信号源電圧をVi 出力電圧をvOとすればした、
かって、このG(!りを入力信号レベルの大小によって
切換えるように制御すれば、第2図に示すように、ノイ
ズ成分を含む信号より゛信号成分のみを取り出す場合に
好適な非線型増幅回路を構成することが可能である。
If the input signal source voltage is Vi and the output voltage is vO, then
If this G(!) is controlled to be switched depending on the magnitude of the input signal level, as shown in Figure 2, a nonlinear amplifier circuit suitable for extracting only the signal component from a signal containing noise components can be created. It is possible to configure

゛ 第3図は、本発明の非線型増幅回路の一実施例を示
すものである。npn )ランジスタQ3.Q4は差動
増幅回路を構成するもので本回路の入力段、pnp +
”ランジスタ9.Q2はカレントミラー回路を構成し、
上記各トランジスタQs 、 Q4のおのおのに対する
負荷である。R1は入力抵抗、!は入力バイアス電源で
ある。トランジスタQ5は出力段のエミツタホロワ回路
の構成体であり、R(Rs、Ik、clは、非線型利得
を決定する抵抗ならびに容量の各素子、Q6.、Q7ハ
ヌイツチングトランジスタ、V+ 、 V2〜は電圧源
である。
3 shows an embodiment of the nonlinear amplifier circuit of the present invention. npn) transistor Q3. Q4 constitutes a differential amplifier circuit, and is the input stage of this circuit, pnp +
”Transistor 9.Q2 constitutes a current mirror circuit,
This is the load for each of the above transistors Qs and Q4. R1 is the input resistance! is the input bias power supply. Transistor Q5 is a component of the output stage emitter follower circuit, R (Rs, Ik, cl are resistor and capacitance elements that determine the nonlinear gain, Q6., Q7 are switching transistors, V+, V2~ are It is a voltage source.

第3図(おいて、入力段のトランジスタQsのベースは
、Xでバイアスされており、入力信号のない平衡状態で
は、トランジスタQb、Qy共にオフするように、V+
 、 V2を設定する。今、vBq4の交流レヘlカV
+ + VBxq7) V!lQ4 > V2  Va
xq6  を満たすような入力レベルで、信号が入力さ
れ゛る場合、トランジスタφ+ Q’はカットオフであ
り、負帰還量を決定する伝達関数G(s)は で決定される。ここで、SCはコンデンサCのインピー
ダンス成分である。したがってこの負帰還型増幅回路全
体の利得は キなる。
In FIG. 3, the base of the transistor Qs in the input stage is biased with
, set V2. Now, vBq4's AC Leheka V
+ + VBxq7) V! lQ4 > V2 Va
When a signal is input at an input level that satisfies xq6, the transistor φ+Q' is cut off, and the transfer function G(s) that determines the amount of negative feedback is determined by: Here, SC is the impedance component of capacitor C. Therefore, the gain of this negative feedback type amplifier circuit as a whole is Q.

次K、VBQ4  (7)交流レヘルがV+ + VB
xq7<VBQ4 。
Next K, VBQ4 (7) AC level is V+ + VB
xq7<VBQ4.

V2− VBXQ6  > VBQ4を満たすような入
力レベルで信号り」入力されると、R5の一端は交流的
に接地されることになり となる。したがって、 となり、低入力レベル時の利得より、大ならし、めるこ
とかできる。
If a signal is input at an input level that satisfies V2-VBXQ6>VBQ4, one end of R5 will be grounded in an alternating current manner. Therefore, the gain can be made larger than the gain at low input level.

すなわち、上述の本実施例非線型増幅回路は、第4図に
示すような人出力持性を持たせることが可能で、前述の
如き、信号処理回路において大きな効力を発揮する。
In other words, the nonlinear amplifier circuit of the present embodiment described above can have the human output characteristics as shown in FIG. 4, and exhibits great effectiveness in the signal processing circuit as described above.

なお、第3図の実施例回路において、トランジスタQb
 、 Q7は、バイポ、−ラトランジスタに限らず、適
当なバイアス条件に設定され九FIT、あるいはダイオ
ード等の非線型スイッチング素子によって置き換えても
、同様の回路機能が実現可能である。
In addition, in the embodiment circuit of FIG. 3, the transistor Qb
, Q7 is not limited to a bipolar transistor or a -ra transistor, but the same circuit function can be realized by replacing it with a nonlinear switching element such as a nine-FIT or a diode set to an appropriate bias condition.

以上、非線型増幅回路につい5ての回路例とその特性を
説明したが、本発明は前述の如き回路中のトランジスタ
をNPN構造のものとPNPIII造のものとに極性を
違えた場合においても、同様に有用な回路構成をなすこ
とが可能である。
Above, five examples of nonlinear amplifier circuits and their characteristics have been explained, but the present invention can also be applied even when the polarity of the transistors in the circuit as described above is changed between NPN structure and PNPIII structure. Similarly useful circuit configurations are possible.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は負帰還型増幅回路の基本原理を示すブロック図
、第2図は同回路で処理する信号の一例を示す図、第3
図は本発明の一実施例における非線型増幅回路の回路図
、第4図は同非線型増幅回路の入出力特性を示す図であ
る。 Ql、Q2.Q7°−°°p n p ) ”) 7ジ
スタ、Q’ + Q’ 。 Q5.Q6・・・・・・npn )ランジスタ、R+・
・・・・・入力抵抗、E・・・・・・入力バイアス電源
、R2,、Rs 、 R4・・・・・・抵抗、C1・・
・・・・容量。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第3図 第4viA Vn =75−
Fig. 1 is a block diagram showing the basic principle of a negative feedback amplifier circuit, Fig. 2 is a diagram showing an example of a signal processed by the circuit, and Fig. 3 is a block diagram showing the basic principle of a negative feedback amplifier circuit.
The figure is a circuit diagram of a nonlinear amplifier circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing input/output characteristics of the nonlinear amplifier circuit. Ql, Q2. Q7°−°°p n p) ”) 7 transistors, Q' + Q'. Q5.Q6... npn) transistors, R+・
...Input resistance, E...Input bias power supply, R2,, Rs, R4...Resistance, C1...
····capacity. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4viA Vn =75-

Claims (1)

【特許請求の範囲】[Claims] 第1及び第2のトランジスタのエミッタ側を共通定電流
源に接続し、前記第1及び第2のトランジスタ間に差動
ベース電圧がバイアスされ、前記第1及び第2のトラン
ジスタの各コレクタ側にカレントミラー回路よりなる一
対の能動素子をそれぞれの負荷となして接続し、わ記第
2のトランジスタのコレクタ信号をエミッタホロワ回路
を介して出力するとともに、この出力を抵抗を通じて前
記第2のトランジスタに負帰還し、かつ、その帰還量を
非線型スイッチング素子により制御し得る構成を有する
ことを特徴と4した非線型増幅回路。
The emitter sides of the first and second transistors are connected to a common constant current source, a differential base voltage is biased between the first and second transistors, and the collector side of each of the first and second transistors is biased between the first and second transistors. A pair of active elements consisting of a current mirror circuit are connected as respective loads, and the collector signal of the second transistor is outputted through the emitter follower circuit, and this output is applied to the second transistor through a resistor. 4. A nonlinear amplifier circuit characterized in that it has a configuration in which feedback is provided and the amount of feedback can be controlled by a nonlinear switching element.
JP56148510A 1981-09-18 1981-09-18 Nonlinear amplifying circuit Granted JPS5848515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56148510A JPS5848515A (en) 1981-09-18 1981-09-18 Nonlinear amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56148510A JPS5848515A (en) 1981-09-18 1981-09-18 Nonlinear amplifying circuit

Publications (2)

Publication Number Publication Date
JPS5848515A true JPS5848515A (en) 1983-03-22
JPS6362132B2 JPS6362132B2 (en) 1988-12-01

Family

ID=15454372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56148510A Granted JPS5848515A (en) 1981-09-18 1981-09-18 Nonlinear amplifying circuit

Country Status (1)

Country Link
JP (1) JPS5848515A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0468606A (en) * 1990-07-04 1992-03-04 Fuji Photo Film Co Ltd Nonlinear variable gain circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0468606A (en) * 1990-07-04 1992-03-04 Fuji Photo Film Co Ltd Nonlinear variable gain circuit

Also Published As

Publication number Publication date
JPS6362132B2 (en) 1988-12-01

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