JPH025917U - - Google Patents
Info
- Publication number
- JPH025917U JPH025917U JP8363188U JP8363188U JPH025917U JP H025917 U JPH025917 U JP H025917U JP 8363188 U JP8363188 U JP 8363188U JP 8363188 U JP8363188 U JP 8363188U JP H025917 U JPH025917 U JP H025917U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- inverter
- capacitors
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の回路図、第２図は
従来の発振回路の一例の回路図である。
１Ａ，１Ｂ…インバータ回路、２，２Ａ…帰還
回路、Ｃ１〜Ｃ３…コンデンサ、Ｌ１…コイル、
Ｑ１〜Ｑ４…トランジスタ、Ｓ１〜Ｓ３…スイツ
チ。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional oscillation circuit. 1A, 1B...Inverter circuit, 2,2A...Feedback circuit, C1 to C3 ...Capacitor, L1 ...Coil,
Q1 to Q4 ...transistors, S1 to S3 ...switches.
Claims (1)
を備えたＣＭＯＳ型の第１及び第２のインバータ
回路と、複数のコンデンサとこれらコンデンサの
少なくとも１つと接続し制御信号によりこれらコ
ンデンサで構成される容量成分の値を切換える第
１のスイツチ回路とを備え、信号出力端子と接続
する入力端と、出力端とをそれぞれ前記第１のイ
ンバータ回路の出力端と入力端とに接続する帰還
回路と、前記制御信号により、高い周波数の信号
を発生するときは前記第１及び第２のインバータ
回路の入力端間を接続し低い周波数の信号を発生
するときは前記第２のインバータ回路の入力端に
所定の電圧を与えてこの第２のインバータ回路を
オフ状態とする第２のスイツチ回路と、高い周波
数の信号を発生するときは前記第１及び第２のイ
ンバータの出力端間を接続し低い周波数の信号を
発生するときはこれら出力端間を切離す第３のス
イツチ回路とを有することを特徴とする発振回路
。 CMOS type first and second inverter circuits each having a pair of first and second transistors, a plurality of capacitors, and a capacitance component connected to at least one of these capacitors and configured by these capacitors according to a control signal. a first switch circuit that switches the value of the inverter circuit, and a feedback circuit that connects an input terminal connected to the signal output terminal and an output terminal to the output terminal and input terminal of the first inverter circuit, respectively; When generating a high frequency signal, the input terminals of the first and second inverter circuits are connected, and when a low frequency signal is generated, a predetermined voltage is applied to the input terminal of the second inverter circuit. a second switch circuit that turns off the second inverter circuit by giving a signal of a high frequency; An oscillation circuit characterized in that it has a third switch circuit that disconnects these output terminals when a signal is generated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8363188U JPH025917U (en) | 1988-06-23 | 1988-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8363188U JPH025917U (en) | 1988-06-23 | 1988-06-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH025917U true JPH025917U (en) | 1990-01-16 |
Family
ID=31308345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8363188U Pending JPH025917U (en) | 1988-06-23 | 1988-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH025917U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04134491U (en) * | 1991-06-05 | 1992-12-15 | 日立化成工業株式会社 | septic tank |
-
1988
- 1988-06-23 JP JP8363188U patent/JPH025917U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04134491U (en) * | 1991-06-05 | 1992-12-15 | 日立化成工業株式会社 | septic tank |
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