JPH02111926U - - Google Patents
Info
- Publication number
- JPH02111926U JPH02111926U JP1932589U JP1932589U JPH02111926U JP H02111926 U JPH02111926 U JP H02111926U JP 1932589 U JP1932589 U JP 1932589U JP 1932589 U JP1932589 U JP 1932589U JP H02111926 U JPH02111926 U JP H02111926U
- Authority
- JP
- Japan
- Prior art keywords
- emphasis
- capacitor
- ground
- output terminal
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Filters And Equalizers (AREA)
Description
第１図は本考案の一実施例のデイエンフアシス
回路の回路図、第２図はその変形例を示す同回路
図、第３図は従来の同回路図、第４図はデイエン
フアシスの周波数特性を示す図である。
Fig. 1 is a circuit diagram of a de-emphasis circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing a modification thereof, Fig. 3 is a conventional circuit diagram, and Fig. 4 shows the frequency characteristics of the de-emphasis circuit. It is a diagram.
Claims (1)
デイエンフアシス特性に共通の第１の抵抗と、出
力端子と接地間に接続される第１のデイエンフア
シス特性用の第１のコンデンサと、出力端子と接
地間に接続される第２のデイエンフアシス特性用
の第２のコンデンサ、第２の抵抗及びスイツチ手
段の直列回路とから構成し、上記スイツチ手段の
切り換えにより第１と第２のデイエンフアシス特
性を切り換えることを特徴とするデイコンフアシ
ス回路。 (2) 上記第１のコンデンサが上記第２のコンデ
ンサよりその値が小さいことを特徴とする実用新
案登録請求の範囲第１項記載のデイエンフアシス
回路。[Claims for Utility Model Registration] (1) A first resistor common to the first and second de-emphasis characteristics connected between the input and output terminals, and the first de-emphasis characteristic connected between the output terminal and ground. a first capacitor for de-emphasis characteristics, a second capacitor for de-emphasis characteristics connected between the output terminal and ground, a second resistor, and a series circuit of switching means, and A de-emphasis circuit characterized by switching between first and second de-emphasis characteristics. (2) The de-emphasis circuit according to claim 1, wherein the first capacitor has a smaller value than the second capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1932589U JPH02111926U (en) | 1989-02-21 | 1989-02-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1932589U JPH02111926U (en) | 1989-02-21 | 1989-02-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02111926U true JPH02111926U (en) | 1990-09-07 |
Family
ID=31234734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1932589U Pending JPH02111926U (en) | 1989-02-21 | 1989-02-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02111926U (en) |
-
1989
- 1989-02-21 JP JP1932589U patent/JPH02111926U/ja active Pending
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