JPS62108007A - Method of dividing semiconductor board - Google Patents

Method of dividing semiconductor board

Info

Publication number
JPS62108007A
JPS62108007A JP60249440A JP24944085A JPS62108007A JP S62108007 A JPS62108007 A JP S62108007A JP 60249440 A JP60249440 A JP 60249440A JP 24944085 A JP24944085 A JP 24944085A JP S62108007 A JPS62108007 A JP S62108007A
Authority
JP
Japan
Prior art keywords
plane
silicon plate
semiconductor
view
semiconductor board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60249440A
Other languages
Japanese (ja)
Inventor
修 佐々木
勝 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP60249440A priority Critical patent/JPS62108007A/en
Publication of JPS62108007A publication Critical patent/JPS62108007A/en
Pending legal-status Critical Current

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  • Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Dicing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】[Detailed description of the invention] 【発明の属する技術分野] 本発明は、半導体板からダイシングにより多数の半導体チップを得る半導体板の分割方法に関する。 【従来技術とその問題点】[Technical field to which the invention pertains] The present invention relates to a method for dividing a semiconductor board to obtain a large number of semiconductor chips by dicing the semiconductor board. [Prior art and its problems]

小型の半導体素子の製造の際、円形のシリコン板をダイ
シングして角形の半導体チップに分割する工程がある。 この工程は、ダイヤモンド粉と金属粉とを混ぜて焼結し
てつくった円板形のダイヤモンドブレードを高回転させ
て、第2図(alおよびそのA−A線断面図(blに示
すようにシリコン板1に一方向に平行な溝21を形成し
、次いで第2図+C1およびそのB−BvA断面図fd
+に示すように直角方向に平行な溝22を形成する溝切
り工程と、このシリコン板1に第2図(el、 (fl
のように曲げ力25を加えて個々の半導体チップ2に分
割する工程とからなる。 シリコン板には(111)、 (110)、 (100
)の3種類の結晶面を有するものが用いられる。第3図
に示すようにシリコン板の表面31が(100)面であ
る場合には、へき開面である(011)面32. (0
11)面33が(100)面と90″であるため、第2
図[elのように力を加えて割る場合簡単にへき開して
、第3図(alのC−C線、D−D線断゛面図である第
3図中1.(C)に示すように表面に垂直な側面32.
33を有する角形チップ2を得ることができる。しかし
、第、1図に示しているシリコン板1の表面31が(1
11)面であるときは、(110)へき開面34は表面
31に対して垂直であるが、(011)へき開面ば表面
31に対して30゜の角度であるため、面34に直角に
(TT2)面35にはへき関せずに(OTI)面36に
へき関する。また、第5図に示しているシリコン板1の
表面31が(110)面であるときは、(110)へき
開面36は表面31に対して90°の角度にあるが、(
011)へき開面ば表面31に対して45°の角度にあ
る。そのため分割のときに第5図(blに示すように(
001)面37にはへき関せず、(Ojl)面38でへ
き間する。従って第2図に示した溝21を(110)面
に、溝22を(001)面に入れると、第6図18+に
示すようにへき関し、得られる千ノブは第6回出)に示
すように(110)面の面31と溝21により形成され
る(001)面37とその下の表面に45°の角をなす
(Oll)面38と422により形成される(110)
面36とにより囲まれている。第4図に示シた(111
)ウェハの場合も同様である。こノヨうIZ分割される
結果、チップ形状不良やパンケージング不良となり、さ
らに分割時発生したマイクロクラッチ等の欠陥により、
特に下面側にもパターンを形成する場合には信頼性の低
下を引きおこす。 この対策としてシリコン板の厚さ全体をダイヤ−モンド
プレードで突き切るフルカットを行うことが考えられる
。しかしシリコン板を真空チャックにより基台上に固定
してフルカットすると、吸込口の上に存在しないチップ
が飛散してしまう、これを避けるため接着剤、粘1テー
プ等でシリコン板を基台上に固定する方法も考えられる
が、チップ表面に接着剤か残り、それ以後の組立工程の
支障となる。
When manufacturing small semiconductor devices, there is a step of dicing a circular silicon plate to divide it into square semiconductor chips. In this process, a disc-shaped diamond blade made by mixing and sintering diamond powder and metal powder is rotated at high speed, A groove 21 parallel to one direction is formed in the silicon plate 1, and then Fig. 2 +C1 and its B-BvA sectional view fd
2 (el, (fl
It consists of a step of dividing into individual semiconductor chips 2 by applying a bending force 25 as shown in FIG. The silicon plate has (111), (110), (100
) having three types of crystal planes are used. As shown in FIG. 3, when the surface 31 of the silicon plate is the (100) plane, the (011) plane 32. which is the cleavage plane. (0
11) Since the plane 33 is 90″ from the (100) plane, the second
When breaking by applying force as shown in Figure [el], it is easily cleaved and shown in Figure 3 (1.(C) in Figure 3, which is a cross-sectional view of The side surface perpendicular to the surface 32.
A square chip 2 having a diameter of 33 can be obtained. However, if the surface 31 of the silicon plate 1 shown in FIG.
11) plane, the (110) cleavage plane 34 is perpendicular to the surface 31, but since the (011) cleavage plane is at an angle of 30° to the surface 31, the (110) cleavage plane 34 is perpendicular to the plane 34. TT2) is connected to the (OTI) surface 36 without being connected to the surface 35. Further, when the surface 31 of the silicon plate 1 shown in FIG. 5 is a (110) plane, the (110) cleavage plane 36 is at an angle of 90° to the surface 31, but
011) The cleavage plane is at an angle of 45° to the surface 31. Therefore, when dividing, as shown in Figure 5 (bl)
It is not separated from the (001) plane 37 but separated by the (Ojl) plane 38. Therefore, if the groove 21 shown in Fig. 2 is placed in the (110) plane and the groove 22 is placed in the (001) plane, they will be separated as shown in Fig. 6 18+, and the obtained thousand knobs will be shown in the 6th entry). The (001) plane 37 is formed by the (110) plane 31 and the groove 21, and the (110) plane is formed by the (Oll) planes 38 and 422 that form a 45° angle with the surface below it.
It is surrounded by a surface 36. As shown in Figure 4 (111
) The same applies to wafers. As a result of this IZ splitting, defective chip shapes and poor pancasing occur, and furthermore, due to defects such as micro clutches that occur during splitting,
Particularly, when a pattern is formed also on the lower surface side, reliability decreases. As a countermeasure to this problem, it is conceivable to perform a full cut by cutting through the entire thickness of the silicon plate with a diamond blade. However, if the silicon plate is fixed on the base with a vacuum chuck and then fully cut, chips that are not present on the suction port will scatter.To avoid this, the silicon plate is placed on the base with adhesive or adhesive tape. A method of fixing the chip to the chip surface could also be considered, but some adhesive would remain on the chip surface, which would interfere with the subsequent assembly process.

【発明の目的】[Purpose of the invention]

本発明は、上述の問題を解決して基台上に真空チャック
により固定した半導体板をその両面にへき開の影響を生
ずることのないようにグイシングすることのできる半導
体板の分割方法を提供することを目的とする。
The present invention solves the above-mentioned problems and provides a method for dividing a semiconductor board, which is capable of guising a semiconductor board fixed on a base by a vacuum chuck without causing any cleavage effects on both sides of the semiconductor board. With the goal.

【発明の要点】[Key points of the invention]

本発明は、半導体板の両面から対向する位置に少なくと
も二方向の平行溝を形成して板厚の中央部分を残し、次
いで仮に曲げ応力を与入ることにより両面近傍にへき開
の影響が生ずることのないようにチップに分割するもの
で、溝切り時にはチップに分離されないため真空チャッ
クの使用が可能であり、上記の目的が達成される。
The present invention forms parallel grooves in at least two directions at opposing positions on both sides of a semiconductor board, leaving a central part of the board thickness, and then applying bending stress to prevent the effect of cleavage from occurring near both sides. Since it is not separated into chips during grooving, it is possible to use a vacuum chuck, and the above purpose is achieved.

【発明の実施例】[Embodiments of the invention]

第1図は本発明の一実施例を示すもので、まず第1図1
alに示すようにシリコン板1の裏面12にダイヤモン
ドブレードで平行溝23を形成し、次いで第1回出)に
示すように溝23と直角の溝24を形成する。第1図(
Mlは第1回出)の■−■線断面図を示す。 次に第1図(01,+d)に示すようにシリコン板1の
表面11の溝23の反対側に溝21を、溝24の反対側
に溝22を形成する。第1図(flは第1図(a)のJ
−JvA断面を示す。このシリコン板を第2図(81,
<1)のように曲げ力を加えると、シリコン板lの表面
および溝の形成面の結晶面の如何にかかわらず、対向す
る=溝21と23.22と24の間の薄い部分に複雑な
へき開面3が生じ、分割されたチップ2の中までへき開
が伸びることがない、シリコン板1は曲げ力を加えるま
では溝の間の薄い部分によってつながっているため、溝
切りを真空チャックにより固定したシリコン板に対して
行うことができる。また、へき開は板厚の中央部で起こ
るため、両面から半導体素子の拡散パターンを形成する
場合にも影響を与えることがなく、素子の信頼性を向上
させる。 両面の溝21〜24は表面側の溝21.22から先に形
成しても同じ効果が得られることはもちろんである。ま
た溝の形成はダイヤモンドブレードに限らず、ダイヤモ
ンドツールあるいはダイヤモンドスクライバを用いて行
ってもよい。
FIG. 1 shows one embodiment of the present invention.
Parallel grooves 23 are formed on the back surface 12 of the silicon plate 1 using a diamond blade as shown in FIG. Figure 1 (
Ml shows a sectional view taken along the line ■-■. Next, as shown in FIG. 1 (01, +d), a groove 21 is formed on the side opposite to the groove 23 on the surface 11 of the silicon plate 1, and a groove 22 is formed on the opposite side to the groove 24. Figure 1 (fl is J in Figure 1 (a)
- Shows the JvA cross section. This silicon plate is shown in Figure 2 (81,
When bending force is applied as shown in <1), regardless of the crystal plane of the surface of the silicon plate l and the surface where the grooves are formed, a complicated A cleavage plane 3 is generated, and the cleavage does not extend into the divided chip 2. The silicon plate 1 is connected by the thin part between the grooves until bending force is applied, so the groove cut is fixed by a vacuum chuck. It can be performed on a silicon plate. Furthermore, since the cleavage occurs at the center of the plate thickness, it does not affect the formation of the diffusion pattern of the semiconductor element from both sides, improving the reliability of the element. Of course, the same effect can be obtained even if the grooves 21 to 24 on both sides are formed first, starting with the grooves 21 and 22 on the front side. Further, the grooves are not limited to be formed using a diamond blade, but may be formed using a diamond tool or a diamond scriber.

【発明の効果】 本発明によれば、半導体板の両面から対向する溝を半導
体板を切断してしまわない程度に入れてグイシングする
もので、半導体板表面および分割面の結晶面に関係なく
、例えば互いに垂直な面で囲まれた角形半導体チップを
得ることができ、半導体チップ、特にその両面近傍への
へき開の影響を少なくし、チップ形状不良、パンケージ
ング不良あるいは特性不良を少なくし、半導体素子の製
造の歩留り、でき上がった半導体素子の信頼性を向上さ
せるのに有効である。
Effects of the Invention According to the present invention, grooves facing each other from both sides of the semiconductor board are inserted to the extent that the semiconductor board is not cut, and guising is performed, regardless of the crystal plane of the semiconductor board surface and the dividing plane. For example, it is possible to obtain a rectangular semiconductor chip surrounded by mutually perpendicular surfaces, which reduces the influence of cleavage on the semiconductor chip, especially near both sides, reduces chip shape defects, pancaging defects, or characteristic defects, and improves the semiconductor element. It is effective in improving the manufacturing yield of semiconductor devices and the reliability of finished semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示し、tel、 (bl、
 (C)。 (dlは溝形成工程を順次示す平面図、(elはfat
のI−1線、(f)は(alのJ−Jg断面図、第2図
は従来のグイシング工程を順次示し、(blはtalの
A−A線、(d)は(01のB−B!断面図、tel、
 (f)は分割時の断面図、第3図は従来のダイシング
による(100)ウェハの分割例を示し、(alは平面
図、 (blは(alのC−C&I。 (dlは(alのD −D 4%断面図、第4図は従来
のダイシングによる(Ill)ウェハの分割例を示し、
(a)は平面図、(blはtalのE−El、(clは
+1mlのF−F線断面図、第5図は従来のダイシング
による(110)ウェハの分割例を示し、(4)は平面
図、山)は(alのG−G線、(C)は(シ)のH−H
線断面図、第6図は第5図の分割例の拡大図で、t8)
はへき開の生成を示す断面図、伽)は得られたチップの
斜視図である。 1:シリコン板、11.127板面、2:チップ、21
、22.23.24F溝、3:へき開面。 (c)(d) 第1図 [有])(C) Cb)               (d)(f) 第2図 第3図 (υ             (c)第4図 (Q)
FIG. 1 shows an embodiment of the present invention, tel, (bl,
(C). (dl is a plan view sequentially showing the groove forming process, (el is fat
(f) is a J-Jg sectional view of (al), Figure 2 shows the conventional guissing process in sequence, (bl is a line A-A of tal, (d) is a B-- B! Cross section, tel.
(f) is a cross-sectional view at the time of division, and FIG. 3 shows an example of division of a (100) wafer by conventional dicing, (al is a plan view, (bl is C-C&I of (al). (dl is (al of D-D 4% cross-sectional view, FIG. 4 shows an example of dividing a (Ill) wafer by conventional dicing,
(a) is a plan view, (bl is E-El of tal, (cl is +1 ml cross-sectional view on line F-F), FIG. 5 shows an example of dividing a (110) wafer by conventional dicing, and (4) is Plan view, mountain) is line GG of (al), (C) is line H-H of (shi)
Line sectional view, Figure 6 is an enlarged view of the division example in Figure 5, t8)
A cross-sectional view showing the formation of cleavages; Figure 3) is a perspective view of the resulting chip. 1: Silicon plate, 11.127 plate surface, 2: Chip, 21
, 22.23.24F groove, 3: Cleavage plane. (c) (d) Figure 1 [Yes]) (C) Cb) (d) (f) Figure 2 Figure 3 (υ (c) Figure 4 (Q)

Claims (1)

【特許請求の範囲】[Claims] 1)半導体板の両面から対向する位置に少なくとも二方
向の平行溝を形成して板厚の中央部分を残し、次いで板
に曲げ応力を与えることを特徴とする半導体板の分割方
法。
1) A method for dividing a semiconductor board, which comprises forming parallel grooves in at least two directions in opposing positions from both sides of the semiconductor board, leaving a central portion of the board thickness, and then applying bending stress to the board.
JP60249440A 1985-11-07 1985-11-07 Method of dividing semiconductor board Pending JPS62108007A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60249440A JPS62108007A (en) 1985-11-07 1985-11-07 Method of dividing semiconductor board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60249440A JPS62108007A (en) 1985-11-07 1985-11-07 Method of dividing semiconductor board

Publications (1)

Publication Number Publication Date
JPS62108007A true JPS62108007A (en) 1987-05-19

Family

ID=17192997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60249440A Pending JPS62108007A (en) 1985-11-07 1985-11-07 Method of dividing semiconductor board

Country Status (1)

Country Link
JP (1) JPS62108007A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001319899A (en) * 2000-05-11 2001-11-16 Disco Abrasive Syst Ltd Dividing method of semiconductor wafer
JP2002252185A (en) * 2001-02-23 2002-09-06 Matsushita Electric Ind Co Ltd Method of manufacturing nitride semiconductor chip
JP2008159959A (en) * 2006-12-26 2008-07-10 Sanyo Electric Co Ltd Method for breaking semiconductor substrate, breaking device, method for breaking solar cell, and method for fabrication of solar cell module
JP2011181770A (en) * 2010-03-02 2011-09-15 Fuji Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device
JP2018103336A (en) * 2016-12-28 2018-07-05 信越化学工業株式会社 Method for multiple cutoff machining of rare earth sintered magnet
CN114454359A (en) * 2021-07-13 2022-05-10 青岛高测科技股份有限公司 Silicon rod cutting method, device and system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001319899A (en) * 2000-05-11 2001-11-16 Disco Abrasive Syst Ltd Dividing method of semiconductor wafer
JP4590064B2 (en) * 2000-05-11 2010-12-01 株式会社ディスコ Semiconductor wafer dividing method
JP2002252185A (en) * 2001-02-23 2002-09-06 Matsushita Electric Ind Co Ltd Method of manufacturing nitride semiconductor chip
JP4710148B2 (en) * 2001-02-23 2011-06-29 パナソニック株式会社 Manufacturing method of nitride semiconductor chip
JP2008159959A (en) * 2006-12-26 2008-07-10 Sanyo Electric Co Ltd Method for breaking semiconductor substrate, breaking device, method for breaking solar cell, and method for fabrication of solar cell module
JP2011181770A (en) * 2010-03-02 2011-09-15 Fuji Electric Co Ltd Semiconductor device and method of manufacturing semiconductor device
US9355858B2 (en) 2010-03-02 2016-05-31 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
JP2018103336A (en) * 2016-12-28 2018-07-05 信越化学工業株式会社 Method for multiple cutoff machining of rare earth sintered magnet
CN114454359A (en) * 2021-07-13 2022-05-10 青岛高测科技股份有限公司 Silicon rod cutting method, device and system
CN114454359B (en) * 2021-07-13 2024-05-14 青岛高测科技股份有限公司 Silicon rod cutting method, device and system

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