JPH02105405A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02105405A
JPH02105405A JP25865688A JP25865688A JPH02105405A JP H02105405 A JPH02105405 A JP H02105405A JP 25865688 A JP25865688 A JP 25865688A JP 25865688 A JP25865688 A JP 25865688A JP H02105405 A JPH02105405 A JP H02105405A
Authority
JP
Japan
Prior art keywords
chip
semiconductor
semiconductor device
semiconductor chip
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25865688A
Other languages
Japanese (ja)
Inventor
Kenji Oka
健次 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25865688A priority Critical patent/JPH02105405A/en
Publication of JPH02105405A publication Critical patent/JPH02105405A/en
Pending legal-status Critical Current

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  • Dicing (AREA)

Abstract

PURPOSE:To reduce a crack and a breakage at a chip end and to shorten a distance from the chip end to an element part by chamfering the chip end. CONSTITUTION:A groove 12 is dug in a semiconductor substrate 11 by using a diamond grindstone; in succession, the groove is dug so as to reach its rear; a semiconductor chip 13 having a chamfered part 2 is obtained. By this chamfering operation, it is not required to keep a definite distance from a peripheral part when an element is arranged in anticipation of a breakage of a chip end; the chip can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体チップの形状に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the shape of a semiconductor chip.

〔従来の技術〕[Conventional technology]

半導体装置に使われる従来の半導体チップは、第5図(
a)、(b)、(c)に示すように一般に直方体である
。これは半導体チップが1枚の半導体基板に多数の半導
体チップを形成した後、ダイヤモンド回転砥石で切断す
る工程によって形成されることによる。
A conventional semiconductor chip used in a semiconductor device is shown in Figure 5 (
As shown in a), (b), and (c), it is generally a rectangular parallelepiped. This is because semiconductor chips are formed by a process in which a large number of semiconductor chips are formed on one semiconductor substrate and then cut using a diamond rotating grindstone.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが上述の半導体チップはチップ周辺に割れや欠け
が生じやすい。なぜなら、半導体そのものは硬いがもろ
いという性質を持っているから、直角に加工するとどう
しても角で割れや欠けが生じてしまう。この割れや欠け
は第1には製造工程中に生じる。ダイヤモンド砥石での
切断工程で生じやすい。第2には完成した半導体装置を
使用中に生じる。使用時の熱や機械的応力が加わりチッ
プ周辺に周囲の樹脂から応力が力qわるためである。
However, the above-mentioned semiconductor chip is prone to cracks and chips around the chip. This is because semiconductors themselves are hard but brittle, so if they are processed at right angles, cracks or chips will inevitably occur at the corners. These cracks and chips first occur during the manufacturing process. This tends to occur during the cutting process with a diamond grindstone. The second problem occurs during use of the completed semiconductor device. This is because heat and mechanical stress are applied during use, and stress from the surrounding resin is applied to the periphery of the chip.

半導体チップに割れや欠けが生じると、その部分に形成
した半導体素子は不良となり半導体装置が動作不良とな
る。これを防ぐためチップ周辺から一定距離(およそ4
0〜50μm)は素子を配置しない様にしている。本発
明の目的は、上述の従来の欠点を除去した半導体装置を
提供することである。
When a crack or chip occurs in a semiconductor chip, the semiconductor element formed in that part becomes defective, and the semiconductor device malfunctions. To prevent this, a certain distance (approximately 4
0 to 50 μm), no elements are arranged. An object of the present invention is to provide a semiconductor device that eliminates the above-mentioned conventional drawbacks.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による半導体装置は、半導体チップ周辺部のチッ
プ主表面とチップ側面とが形成するチップ主表面端を面
とりしたことを特徴とする。
The semiconductor device according to the present invention is characterized in that the end of the main surface of the chip formed by the main surface of the chip and the side surface of the chip in the peripheral area of the semiconductor chip is chamfered.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)は本発明の一実施例を示す半導体チップの
平面図、第1図(b)は第1図(a)のAA′断面図、
第1図(c)は第1図(b)のチップ端部の拡大図であ
る。第1図(c)で明らかな様に本実施例では半導体チ
ップ1の端部に面取り部2が設けである。従来の半導体
チップは、第5図(c)で明らかな様にチップ端は面取
りしてなく直角のままであった。
FIG. 1(a) is a plan view of a semiconductor chip showing one embodiment of the present invention, FIG. 1(b) is a sectional view taken along line AA' in FIG. 1(a),
FIG. 1(c) is an enlarged view of the chip end portion of FIG. 1(b). As is clear from FIG. 1(c), a chamfered portion 2 is provided at the end of the semiconductor chip 1 in this embodiment. As is clear from FIG. 5(c), conventional semiconductor chips have chip edges that are not chamfered and remain at right angles.

本実施例の製造方法を第2図に示す。第2図(a)の半
導体基板11にダイヤモンド砥石を用いて第2図(b)
のように清12を堀り、続いて第2図(c)のように溝
を裏面に到達させることで面取りを行なって半導体チッ
プ13を得ることができる。
The manufacturing method of this example is shown in FIG. 2(b) using a diamond grindstone on the semiconductor substrate 11 of FIG. 2(a).
The semiconductor chip 13 can be obtained by digging the hole 12 as shown in FIG.

また、−度の研削でもダイヤモンド回転砥石14の断面
形状を第3図(b)に示す様に工夫することで第3図(
a)の半導体基板11から直ちに第3図(c)に示す面
取りを行なった半導体チップ13が得られる。
In addition, even in -degree grinding, the cross-sectional shape of the diamond rotary grindstone 14 can be devised as shown in FIG. 3(b).
A chamfered semiconductor chip 13 as shown in FIG. 3(c) is immediately obtained from the semiconductor substrate 11 of a).

第4図は本発明の半導体チップの他の製造方法を示す。FIG. 4 shows another method of manufacturing the semiconductor chip of the present invention.

この方法では面取りを研削の前に行なう。すなわち、第
4図(a)の半導体基板21のチップ端子室部分にあら
かじめ溝22を形成しておく。溝の形成の方法は化学的
に半導体をエツチングしてもよいし、物理的にプラズマ
エツチング等で形成してもよい。選択的にチップ端子室
部分をエツチングするには写真蝕刻法を用いる。その後
従来法と同様に第4図(c)のように切断して半導体チ
ップ23を得る。この方法では面取り部に応力が残らな
く、また面取り部も正確に加工できる利点がある。
In this method, chamfering is performed before grinding. That is, the groove 22 is previously formed in the chip terminal chamber portion of the semiconductor substrate 21 shown in FIG. 4(a). The grooves may be formed by chemically etching the semiconductor or physically by plasma etching or the like. A photolithography method is used to selectively etch the chip terminal chamber portion. Thereafter, as in the conventional method, the semiconductor chip 23 is obtained by cutting as shown in FIG. 4(c). This method has the advantage that no stress remains on the chamfered portion and that the chamfered portion can also be processed accurately.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はチップ端に面取りを行なう
ことによりチップ端の割れ、欠けが少なくなり、チップ
端と素子部分までの距離を縮めることができ、チップ縮
小を図ることができ、コストダウンになる。また組立後
の信頼度も向上する。
As explained above, by chamfering the chip end, the present invention reduces cracking and chipping of the chip end, reduces the distance between the chip end and the element part, reduces the size of the chip, and reduces costs. become. It also improves reliability after assembly.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明の一実施例の平面図、第1図(b
)は第1図(a>のA−A’断面図、第1図(c)は第
1図(b)の断面図の部分拡大図、第2図(a)、(b
)、(c)、第3図(a>、(b)、(c)および第4
図(a)。 (b)、(c)は本発明の半導体チップの製造方法を示
す断面図、第5図(a)は従来の半導体チップの平面図
、第5図(b)は第5図(a)のB−B’断面図、第5
図(C)は第5図(b)の部分拡大図である。 1.13,23.33・・・半導体チップ、2・・・面
取り部、11.21・・・半導体基板、12.22・・
・溝、14・・・ダイヤモンド回転砥石。 //〒妻7外巻火 / 1ノ件≦4′、木ゾ分・、ノ。 / 、− 肩 ノf千−1第11版 ノ 図 月 図
FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
) is a cross-sectional view taken along line A-A' in Figure 1 (a), Figure 1 (c) is a partially enlarged view of the cross-sectional view in Figure 1 (b), and Figures 2 (a) and (b) are
), (c), Figure 3 (a>, (b), (c) and Figure 4
Figure (a). (b) and (c) are cross-sectional views showing the method of manufacturing a semiconductor chip of the present invention, FIG. 5(a) is a plan view of a conventional semiconductor chip, and FIG. BB' sectional view, 5th
FIG. 5(C) is a partially enlarged view of FIG. 5(b). 1.13, 23.33... Semiconductor chip, 2... Chamfered portion, 11.21... Semiconductor substrate, 12.22...
・Groove, 14...Diamond whetstone. // 〒 Wife 7 outer volume fire / 1 item ≦ 4', Thu zo minute..., ノ. / , - Shoulder No F Sen-1 11th Edition Tsukizu

Claims (1)

【特許請求の範囲】[Claims] 半導体チップ周辺部のチップ主表面とチップ側面とが形
成するチップ主表面端を面取りしたことを特徴とする半
導体装置。
1. A semiconductor device characterized in that a chip main surface edge formed by a chip main surface and a chip side surface in a peripheral area of the semiconductor chip is chamfered.
JP25865688A 1988-10-13 1988-10-13 Semiconductor device Pending JPH02105405A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25865688A JPH02105405A (en) 1988-10-13 1988-10-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25865688A JPH02105405A (en) 1988-10-13 1988-10-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02105405A true JPH02105405A (en) 1990-04-18

Family

ID=17323281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25865688A Pending JPH02105405A (en) 1988-10-13 1988-10-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02105405A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885522B1 (en) 1999-05-28 2005-04-26 Fujitsu Limited Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation
US7638858B2 (en) 2003-05-16 2009-12-29 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885522B1 (en) 1999-05-28 2005-04-26 Fujitsu Limited Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation
US7347347B2 (en) 1999-05-28 2008-03-25 Fujitsu Limited Head assembly, disk unit, and bonding method and apparatus
US7638858B2 (en) 2003-05-16 2009-12-29 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof

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