JPH01108008A - Cutting of semiconducting wafers - Google Patents

Cutting of semiconducting wafers

Info

Publication number
JPH01108008A
JPH01108008A JP62266762A JP26676287A JPH01108008A JP H01108008 A JPH01108008 A JP H01108008A JP 62266762 A JP62266762 A JP 62266762A JP 26676287 A JP26676287 A JP 26676287A JP H01108008 A JPH01108008 A JP H01108008A
Authority
JP
Japan
Prior art keywords
semiconducting
cutting
wafers
chips
lowermost
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62266762A
Other languages
Japanese (ja)
Inventor
Hiroaki Fujimoto
博昭 藤本
Kenzo Hatada
畑田 賢造
Nobutoshi Takebashi
信逸 竹橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62266762A priority Critical patent/JPH01108008A/en
Publication of JPH01108008A publication Critical patent/JPH01108008A/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To improve a productivity and make a cost-saving by piling up and fixing a plurality of semiconducting wafers, forming cut grooves from the uppermost section to the lowermost section and cutting a plurality of semiconducting wafers at the same time. CONSTITUTION:Semiconducting wafers 1 are piled up and fixed by using adhesive tapes 2. In this case, the cutting lines of each semiconducting wafers 1 are maintained to be aligned each other. Then, by forming cut grooves from the uppermost semiconducting wafer 1 to the lowermost one 1 with a diamond whetstone or a laser, semiconducting chips 4 are obtained. After cutting, the semiconducting chips 4 are taken out by stretching the lowermost adhesive tape 2, and widening the interval between the semiconducting chips 4 and the semiconducting chips 4 are put to use from one which is cut out from the lowermost semiconducting wafer 1. The adhesive tapes 2 remaining on the surface of the second lower and third lower semiconducting chips 4 are removed by using other highly adhesive tapes and peeling.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体ウェハの切断方法に関するもの従来の技
術を第2図とともに説明する。従来の技術としては、ス
クライプ法と、砥石によるダイシング法があるが、ここ
ではダイシング法について説明する。まず、第2図(&
)に示すように、半導体ウェハ21を粘着テープ22に
はり付ける。その後、第2図中)に示すようにダイシン
グソーにより、切断溝23を形成し、最後に、第2図(
0)に示すように、粘着テープ22を引き伸ばし、半導
体チップ24を得るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for cutting semiconductor wafers.A conventional technique will be explained with reference to FIG. Conventional techniques include a scribe method and a dicing method using a grindstone, but the dicing method will be explained here. First, Figure 2 (&
), a semiconductor wafer 21 is attached to an adhesive tape 22. Thereafter, cutting grooves 23 are formed using a dicing saw as shown in FIG.
0), the adhesive tape 22 is stretched to obtain a semiconductor chip 24.

発明が解決しようとする問題点 前記従来例では、半導体ウェハを1枚づつしか処理でき
ず非常に長い時間を要するため、次に示す問題点がある
Problems to be Solved by the Invention In the conventional example described above, since only one semiconductor wafer can be processed and it takes a very long time, there are the following problems.

(1)特に大口径の半導体ウェハにおいては、拡散工程
、エッチング工程等他の工程との時間に関するアンバラ
ンスが生じその結果、切断装置を多数必要とする。
(1) Particularly in the case of large-diameter semiconductor wafers, a time imbalance occurs with other processes such as a diffusion process and an etching process, and as a result, a large number of cutting devices are required.

@)上記の理由により非常にコヌトの高いものとなる。@) Due to the above reasons, it is extremely expensive.

本発明は、半導体ウェハの切断工程の生産性を高め低コ
スト化を図るものである。
The present invention aims to improve productivity and reduce costs in the process of cutting semiconductor wafers.

問題点を解決するための手段 本発明は、前記問題点を解決するために、半導体ウェハ
を複数枚重ねて同時に切断するものである。
Means for Solving the Problems The present invention solves the above problems by stacking a plurality of semiconductor wafers and cutting them simultaneously.

作用 半導体ウェハを複数枚重ねて同時に切断することで、生
産性を高め、低コスト化を図ることができる。
By stacking a plurality of working semiconductor wafers and cutting them simultaneously, productivity can be increased and costs can be reduced.

実施例 本発明の一実施例を第1図と共に説明する。Example An embodiment of the present invention will be described with reference to FIG.

まず、第1図(IL)に示すように、半導体ウェハ1を
、粘着テープ2を用いて重ねて固定する。この時、各々
の半導体ウェハ1の切断ラインは、一致させておく。半
導体ウェハ1の位置合わせは、パターン認識を用いるこ
とにより、精度よく容易に実施できる。次に第1図(b
)に示すように、ダイアモンド砥石あるいは、レーザー
により、最上部の半導体ウェハ1から最下部の半導体ウ
ェハ1に至る、切断溝3を形成し、半導体チップ4を得
る。
First, as shown in FIG. 1 (IL), semiconductor wafers 1 are stacked and fixed using adhesive tape 2. At this time, the cutting lines of each semiconductor wafer 1 are made to coincide. The alignment of the semiconductor wafer 1 can be easily performed with high precision by using pattern recognition. Next, Figure 1 (b
), a cutting groove 3 is formed from the uppermost semiconductor wafer 1 to the lowermost semiconductor wafer 1 using a diamond grindstone or a laser, and a semiconductor chip 4 is obtained.

切断溝3の巾は10〜60μm程度であり、切断溝3の
形成スピードは、60〜200 mu/sea程度であ
る。切断後の半導体チップ4の取り出しは、最下部の粘
着テープ2を引き伸ばし、半導体チップ4の間隔を広げ
た後、最上部の半導体ウェハ1より切り出した半導体チ
ップ4から使用する。粘着テープ1の粘着力は非常に弱
いため、真空コレット等で容易に半導体チップ4を取り
出すことができる。表面から2枚目および3枚目の半導
体ウェハ1から切り出した半導体チップ4の表面に残っ
た粘着テープ2は、強い粘着力をもつ他の粘着テープを
粘着し、その後、180度ピーリングすることにより、
半導体チップ4上の粘着テープ2は容易に除去すること
ができる。本実施例では、半導体ウェハの固定に粘着テ
ープを用いたが、これに限らず、接着剤やワックス等で
もかまわない。
The width of the cutting groove 3 is about 10 to 60 μm, and the forming speed of the cutting groove 3 is about 60 to 200 mu/sea. After cutting, the semiconductor chips 4 are taken out by stretching the lowermost adhesive tape 2 to widen the interval between the semiconductor chips 4, and then the semiconductor chips 4 cut from the uppermost semiconductor wafer 1 are used. Since the adhesive strength of the adhesive tape 1 is very weak, the semiconductor chip 4 can be easily removed using a vacuum collet or the like. The adhesive tape 2 remaining on the surface of the semiconductor chip 4 cut out from the second and third semiconductor wafers 1 from the front surface is removed by attaching another adhesive tape with strong adhesive strength and then peeling it 180 degrees. ,
The adhesive tape 2 on the semiconductor chip 4 can be easily removed. In this embodiment, an adhesive tape is used to fix the semiconductor wafer, but the adhesive tape is not limited to this, and adhesives, wax, etc. may also be used.

発明の効果 以上述べたように本発明では、複数枚の半導体ウェハを
同時に切断できるため、生産性が飛躍的に向上し、大口
径の半導体ウェハにおいても、非常にコストの安い、半
導体を得ることができる。
Effects of the Invention As described above, in the present invention, since multiple semiconductor wafers can be cut simultaneously, productivity is dramatically improved, and semiconductors can be obtained at extremely low cost even from large diameter semiconductor wafers. Can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例方法の工程別断面図、第2
図は従来方法の工程断面図である。 1・・・・・・半導体ウェハ、2・・・・・・粘着テー
プ、3・・・・・・切断溝、4・・・・・・半導体チッ
プ。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名22
−fI**−7・
FIG. 1 is a sectional view of each step of a method according to an embodiment of the present invention, and FIG.
The figure is a process sectional view of a conventional method. 1... Semiconductor wafer, 2... Adhesive tape, 3... Cutting groove, 4... Semiconductor chip. Name of agent: Patent attorney Toshio Nakao and 1 other person22
-fI**-7・

Claims (3)

【特許請求の範囲】[Claims] (1)複数枚の半導体ウェハを重ねて固定し、最上部の
半導体ウェハから最下部の半導体ウェハに至る切断溝を
形成することにより、前記複数枚の半導体ウェハを同時
に切断するようにした半導体ウェハの切断方法。
(1) A semiconductor wafer in which a plurality of semiconductor wafers are stacked and fixed, and a cutting groove is formed from the top semiconductor wafer to the bottom semiconductor wafer so that the plurality of semiconductor wafers can be cut simultaneously. cutting method.
(2)複数枚の半導体ウェハを接着剤あるいは粘着テー
プにより固定した特許請求の範囲第1項記載の半導体ウ
ェハの切断方法。
(2) The method for cutting semiconductor wafers according to claim 1, wherein a plurality of semiconductor wafers are fixed with adhesive or adhesive tape.
(3)切断溝を砥石あるいはレーザーにより形成した特
許請求の範囲第2項記載の半導体ウェハの切断方法。
(3) The method for cutting a semiconductor wafer according to claim 2, wherein the cutting grooves are formed using a grindstone or a laser.
JP62266762A 1987-10-21 1987-10-21 Cutting of semiconducting wafers Pending JPH01108008A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62266762A JPH01108008A (en) 1987-10-21 1987-10-21 Cutting of semiconducting wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62266762A JPH01108008A (en) 1987-10-21 1987-10-21 Cutting of semiconducting wafers

Publications (1)

Publication Number Publication Date
JPH01108008A true JPH01108008A (en) 1989-04-25

Family

ID=17435355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62266762A Pending JPH01108008A (en) 1987-10-21 1987-10-21 Cutting of semiconducting wafers

Country Status (1)

Country Link
JP (1) JPH01108008A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006176403A (en) * 2000-12-15 2006-07-06 Lzh Laserzentrum Hannover Ev Method of starting cut zone
SG129280A1 (en) * 2003-03-11 2007-02-26 Disco Corp Method of dividing a semiconductor wafer
JP2008235723A (en) * 2007-03-22 2008-10-02 Zycube:Kk Wafer body structure and manufacturing method thereof
US7755204B2 (en) 2002-05-08 2010-07-13 Micron Technology, Inc. Stacked die module including multiple adhesives that cure at different temperatures

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006176403A (en) * 2000-12-15 2006-07-06 Lzh Laserzentrum Hannover Ev Method of starting cut zone
US7755204B2 (en) 2002-05-08 2010-07-13 Micron Technology, Inc. Stacked die module including multiple adhesives that cure at different temperatures
SG129280A1 (en) * 2003-03-11 2007-02-26 Disco Corp Method of dividing a semiconductor wafer
JP2008235723A (en) * 2007-03-22 2008-10-02 Zycube:Kk Wafer body structure and manufacturing method thereof

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