JPS6210451B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an asynchronous multi-system majority logic circuit in which each system performs a multi-system logic operation using mutually independent clock pulses.

Conventionally, for example, a triple system majority logic circuit has three sets of identical logic circuits, each logic circuit performs the same operation, and the majority decision of the logic output is taken. It needs to work. Specific examples thereof are shown in FIGS. 1 and 2.

First, the triple majority logic circuit shown in Figure 1 is
The logic circuit LG 1 has two clock pulse generation circuits CP ₁ and CP ₂ , and the switching circuit CH switches the clock pulses to be used and supplies the same clock pulse to the triple logic circuits LG ₁ , LG ₂ , and LG _{3 .} ~ Run LG ₃ synchronously and majority circuit MJ
This is a method in which a triple system majority voting operation is performed. However, this method has the disadvantage that the reliability of the device is low because the switching circuit CH is a single system.

Next _, the triple system majority logic circuit shown _{in FIG} . ₃ , clock pulse generation circuits with phase correction PCP ₁ to PCP ₃ , and majority voting circuits MJ ₁ to MJ ₃ that perform majority voting on clock pulses, and a reference pulse generation circuit CPG ₁ for each system.
~Input the reference pulse created in CPG ₃ to the clock pulse creation circuits PCP ₁ to PCP ₃ of each other system, create synchronized clock pulses while correcting the phase of the clock pulse created for each system, and convert the clock pulses into logic. This is a system in which the signal is supplied to circuits LG ₁ to _{LG 3} to perform triple system majority logic operation.
However, in this method, the majority clock pulse generation circuit 1 generates completely synchronized clock pulses while performing phase correction between the systems, which complicates the circuit configuration, resulting in decreased reliability and difficulty in wiring. There were flaws.

The present invention has independent clock pulses for each system and performs logical operations asynchronously.
It is an object of the present invention to provide an asynchronous multi-system majority logic circuit which can eliminate the drawbacks of the conventional method described above.

In order to achieve the above object, the present invention provides, for each system, a reference pulse generation circuit, a clock pulse generation circuit that divides the reference pulse of this reference pulse generation circuit into a frequency necessary for logic operation, and this clock pulse generation circuit. A multi-system majority logic circuit is provided with a logic circuit that performs a logic operation based on a clock pulse given from a logic circuit, and a logic operation signal output from the logic circuit of each system is applied to a majority decision circuit to take a majority decision. Detecting the number of clock pulses output from the clock pulse generation circuit of the system, and when the number of clock pulses reaches a value corresponding to the maximum logical operation time that is possible for majority voting operation, which is determined by taking into account the frequency accuracy of the reference pulse. Each system is characterized in that each system is provided with a logic operation control circuit that applies an operation control signal based on a majority vote between the detection signal and the same detection signal of another system to the clock pulse generation circuit to perform phase correction.

The content of the present invention will be specifically explained below by taking a triple majority logic circuit as an example.

FIG. 3 is a block diagram of a triple system majority logic circuit according to the present invention, FIG. 4 is a time chart for creating a clock pulse, and FIGS. 5 and 6 are time charts for ensuring triple system logic operation.

As shown in FIG. 3, the triple system majority logic circuit according to the present invention includes a reference pulse generation circuit CPG, a clock pulse generation circuit CP, a logic operation control circuit LGC, and a logic circuit LG for each system 1, 2, and 3. Prepared and configured. MJ is a majority circuit. majority circuit
MJ ensures logical operation by checking the consistency of the operations of at least two of the three circuits of systems 1, 2, and 3.

In the reference pulse generation circuits CPG of each system 1, 2, and 3, reference pulses P ₁ , P ₂ , and P ₃ are constantly generated, as shown in FIG. 4a. The frequencies of the reference pulses P ₁ , P ₂ and P ₃ are n times the clock pulse frequency f required for logic operation, and are selected to be equal to each other.

In the clock pulse generation circuit CP, as shown in Fig. 4b, the reference pulse given from the reference pulse generation circuit CPG of its own system is generated for each system 1, 2, and 3.
By frequency-dividing P ₁ , P ₂ , and P ₃ , clock pulses CL ₁ , CL ₂ , and CL ₃ necessary for logic operations are constantly created.

The logic circuit LG generates a logic operation signal from the clock pulses CL ₁ , CL ₂ , and CL ₃ supplied from the clock pulse generation circuit CP, generates a logic operation start signal b, and sends the logic operation start signal b to the logic operation control circuit. Give to LGC. The logic operation signal is input to the majority circuit MJ, and a majority decision is taken.

The logic operation control circuit LGC includes a logic operation start detection circuit 2, a maximum logic operation detection circuit 3, and a majority decision circuit 4.

The logic operation start detection circuit 2 includes a logic circuit LG.
Detects the logic operation start signal b generated by the logic operation start signal b. When the logic operation start detection circuit 2 detects the logic operation start signal b, the logic operation start detection circuits 2 of each system 1, 2, and 3 output an operation control signal as shown in FIG. 4c.
a ₁ , a ₂ , and a ₃ occur respectively. These operation control signals a ₁ , a ₂ , a ₃ are given to the majority circuit 4 of the own system and the majority circuit 4 of the other system. The majority decision circuit 4 takes a majority decision on the operation control signals a ₁ , a ₂ , and a ₃ of each system, and as shown in FIG.
give to

When the operation control signal amj is input to the clock pulse generation circuit CP from the logic operation control circuit LGC of the own system, the clock pulse generation circuit CP of each system receives the reference pulse of the own system from the time the operation control signal amj is input. When converted to P ₁ (or P ₂ , P ₃ ) and delayed by one pulse, a clock pulse frequency division reset signal as shown in FIG. 4e is generated. With this _clock pulse frequency division reset signal _, as _shown in FIG. CL ₁ , CL ₂ , CL ₃
After that, the clock pulse is created again. As a result, the phases of the clock pulses CL ₁ , CL 2 , CL ₃ of each system 1, ₂ , 3 are corrected.

At the start of logic operation, after performing phase correction as described above, clock pulses CL ₁ , CL ₂ , CL ₃
The logic circuits LG of each system 1, 2, and 3 perform the same operation using the logic operation signal created based on secure.

As described above, the clock pulses CL ₁ , CL ₂ , CL ₃ of each system 1, 2, 3 undergo phase correction every time the operation control signal amj is input, but the clock pulses CL ₁ , CL ₂ , CL ₃ The reference pulses P ₁ , P 2 , P 3 of the reference pulse generation circuit CPG, which are provided independently for each system 1, ₂ , and ₃ , are Since the clock pulses are created by dividing the frequency by n by the clock pulse creation circuit CP, depending on the frequency accuracy of each reference pulse P ₁ , P ₂ , P ₃ , the clock pulses shown in FIG. Thus, the systems have a mutual phase of Δt (maximum 1/n).

During phase correction, the clock pulses CL ₁ , CL ₂ , CL ₃ corrected to the phase of △t are the reference pulses P ₁ , P ₂ ,
P ₃ The phase difference increases over time due to mutual frequency accuracy.

Now, assuming that the reference pulses P ₁ , P ₂ and P ₃ have an accuracy of ±1×10 ^-5 , when the number of clock pulses reaches m, each system 1,
The clock pulse phase difference T between 2 and 3 is T=△t+2｜F×1×10 ^-5 |×n×m
......(1) Where F: Reference pulse frequency n: Frequency division ratio m: Number of clock pulses △t: Phase difference during phase correction.

Since the logic operation in the logic circuit LG is performed based on the clock pulses CL ₁ , CL ₂ , and CL ₃ , the occurrence of the above-mentioned phase difference T in the clock pulses CL ₁ , CL ₂ , and CL ₃ means that each system 1,
This means that the logic operations 2 and 3 are also performed with a time difference corresponding to this phase difference T. Therefore, it is necessary to keep the clock pulse phase difference T within a range that allows triple system logic operation. The maximum logic operation detection circuit 3 detects such maximum logic operation time. Next, how to determine the maximum logical operation time will be explained.

Triple system logic operation consists of logic circuits 1, 2, and 3 for each system.
This method ensures logical operation by making the LGs perform the same operation and checking that the operations of at least two of the three circuits match in the majority circuit MJ.In the operation of the present invention, which operates asynchronously, first, It is necessary to satisfy the conditions shown in the figure.

First, as shown in FIG.
If the operation check timing is set at the midpoint of CL ₁ , CL ₂ , and CL ₃ , then the logic must be such that at least two of the three circuits will match the operation at the operation check timing of each system 1, 2, and 3. A motion difference T ₁ is defined. In order to ensure a series of logical operations, the number m of clock pulses is determined so that the clock pulse phase difference T in equation (1) is within the operation difference _T1 . In other words, the number m of clock pulses is determined such that T ₁ ≦△t+2|F×1×10 ^-5 |×n×m.

The maximum logic operation detection circuit 3 detects the number m of clock pulses that satisfies the above-mentioned conditions, and supplies the detected signals as operation control signals a ₁ , a ₂ , and a ₃ to the majority circuits 4 of the own system and other systems. The majority decision circuit 4 outputs an operation control signal amj as a result of the majority decision.
is given to the clock pulse generation circuit CP. Then, the phase correction operation as explained in FIG. 4 is applied to the clock pulse generation circuit CP of each system by the operation control signal amj, and the phase is corrected. This eliminates out-of-phase due to the frequency accuracy of the reference pulse between systems, making it possible to operate stably.

Next, as shown in FIG. 6a and b, a logic operation signal of standard code width consisting of k clock pulses CL ₁ , CL ₂ , CL ₃ is generated as shown in FIG. 6c.
When using the majority vote as a transmission code, a code distortion width T ₂ that satisfies the following equation (2) is determined.

Standard code width - transmission code width (standard code width - T ₂ ) / standard code width + transmission distortion < maximum allowable distortion (2) If one standard transmission code is composed of k clock pulses, then the above For the operating difference T ₁ ,
The above-mentioned T ₂ must satisfy T ₂ ≧k·T ₁ , and the number m of clock pulses mentioned above is determined to satisfy this.

In the embodiment, a triple majority logic circuit is described, but the present invention can be similarly applied to a circuit having a higher number of systems.

As described above, the present invention detects the number of clock pulses output from the clock pulse generation circuit of its own system in an asynchronous multiple system majority logic circuit, and determines the number of clock pulses by taking into account the frequency accuracy of the reference pulse. When the value corresponds to the maximum logic operation time that is determined by the majority decision operation, an operation control signal based on the majority decision between that detection signal and the same detection signal from another system is given to the clock pulse generation circuit to correct the phase. Since each system is equipped with a logic operation control circuit for performing the same operation, it provides a multi-system majority logic circuit that is asynchronous, has a relatively simple circuit configuration, operates stably, and has extremely high reliability. can do.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of a conventional triple system majority logic circuit, Figure 3 is a block diagram of a multiplex majority logic circuit according to the present invention, and Figures 4a to 4e are time charts for creating clock pulses. , Figure 5a
-c and FIGS. 6a to 6c are time charts for ensuring the operation. CPG...Reference pulse generation circuit, CP...Clock pulse generation circuit, LG...Logic circuit, LGC...
Logic operation control circuit.

Claims (1)

[Claims] 1. For each system, a reference pulse generation circuit, a clock pulse generation circuit that divides the reference pulse of this reference pulse generation circuit into a frequency necessary for logic operation, and a clock pulse provided from this clock pulse generation circuit. A multi-system majority logic circuit is provided with a logic circuit that performs a logical operation based on the logic circuit of each system, and a logic operation signal output from the logic circuit of each system is given to a majority circuit to take a majority decision. The number of clock pulses output from the clock pulse generation circuit is detected, and when the number of clock pulses reaches a value corresponding to the maximum logic operation time that allows majority voting operation, which is determined by taking into account the frequency accuracy of the reference pulse, the detection signal is generated. 1. A multi-system majority logic circuit, characterized in that each system is provided with a logic operation control circuit that applies an operation control signal based on a majority vote between the same detection signal and the same detection signal from another system to the clock pulse generation circuit to perform phase correction. 2. The logic operation control circuit performs the operation at the start of operation using an operation control signal obtained from an operation start signal applied from the logic circuit of its own system and an operation control signal based on a majority vote of an operation control signal applied from another system. A multiplex majority logic circuit according to claim 1, characterized in that a phase correction is applied to the clock pulse generation circuit.