JPS628636A - Frame synchronizing device - Google Patents

Abstract

PURPOSE:To obtain a signal shifted surely by one bit even when a reference clock pulse has a comparatively high frequency by using a frequency division circuit to frequency-divide the reference clock pulse and applying comparison/ synthesis with a synchronizing dissident pulse. CONSTITUTION:When a synchronization dissident pulse 21 is outputted continuously for a prescribed number of times, an output 51 of a synchronization protection circuit 5 changes from a high level to a low level. Then a synchronization dissident pulse 21 passes through a NOR gate 4 and is inputted to a OR gate 1700 of a synthesis circuit 17. The reference clock 3 is frequency-divided by a frequency division circuit 16, an output signal 41 of the NOR gate 4 and an output signal 161 of the frequency division circuit 16 are inputted to the OR gate 1700, where they are ORed and the result is inputted to a frame counter as a synthesis signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization device provided in a transmission path for transmitting time-division multiplexed digital signals.

[Conventional technology]

In the time division multiplex transmission system, the output signals of multiple channels to be multiplexed are each inserted at a predetermined position in one frame (a signal string of a fixed length including a frame synchronization pulse), and then sent to the transmission path. Sent out. On the receiving side, after identifying the frame synchronization pulse, a multiplexing/demultiplexing gate is used to separate the signal into each channel and perform processing such as destuffing.

A frame synchronizer is used to identify this frame synchronization pulse.

In a frame synchronization device, a frame synchronization pulse included in a frame is compared with a reference frame pulse generated within the device to identify the frame. That is, the frame synchronization pulse and the reference frame pulse are compared every frame input cycle, and when the two match, it is determined that synchronization has been achieved. Then, a timing pulse is output in order to perform a switching operation of the synchronous separation gate.

FIG. 4 is a block diagram showing an example of a conventional frame synchronization device.

The time-division multiplexed digital signals are transmitted through the transmission path 1 from the left to the right in the figure. This digital signal is input from the transmission line 1 to the synchronization code detection circuit 2 through the branch line 1°. A reference clock pulse 3 is input to the synchronization code detection circuit 2 for timing the operation of each part of the apparatus. The synchronization code detection circuit 2 internally generates a frame pulse for verification, and identifies each frame input through the branch line 11. Then, when a mismatch with the frame pulse for frame synchronization pulse comparison is detected, a synchronization mismatch pulse 21 is output.

This synchronization mismatch pulse 21 is input to a NOR gate 4 and a synchronization protection circuit 5. Synchronous protection circuit 5
is a circuit that changes the gate control signal 5° from high level "H" to low level "L" when the synchronization mismatch pulse 21 is inputted consecutively for a predetermined number of times or more. Normally, in a frame synchronizer, once synchronization is established, even if there is a momentary mismatch in frame pulses due to a code error in the transmission path, etc., it is not judged as a synchronization mismatch, but only when this continues, it is considered as a synchronization mismatch. Perform predetermined processing.

For this purpose, this synchronization protection circuit 5 is provided.

The output signal 41 of the gate 4 is inputted together with the reference clock pulse 3 to an OR gate 6, where the logical sum is taken and inputted to the frequency divider circuit 7. The frequency dividing circuit 7 divides the frequency of the signal by two and outputs the divided signal to the frame counter 8. The frame counter 8 further divides the frequency of this signal as necessary to generate timing pulses 81 to 8 . Output. In this example, it is assumed that four channels of digital signals are multiplexed,
It is configured to output four types of timing pulses. For example, if the frequency of the 4-channel multiplexed digital signal transmitted through the transmission path 1 is 400 mechahertz (:MH,), each timing pulse 8I to 84 output from the frame counter 8 has a frequency of 100MHz.
becomes. Therefore, the signal output from the OR gate 6 is finally frequency-divided by four in the frequency dividing circuit 7 or the frame counter 8 and used.

A time chart of the operation of this device is shown in FIG. 5, which will be explained in conjunction with FIG.

In this device, a synchronization code detection circuit 2 detects a synchronization mismatch, and a synchronization mismatch pulse 2. When (a) in FIG. 5 is output continuously, before this reaches the number of -steps (before the time indicated by the arrow T in FIG. 5), the gate control signal 51 (see FIG. 5 b) is at a high level. In this case, the output signal 41 of the NOR gate 4 is always at a low level (FIG. 5C) and is input to the OR circuit 6.

The OR circuit 6 combines this with the reference clock pulse 3 (Fig. 5d).
) and a signal 6. with the same content as the reference clock pulse 3. (Fig. 5e) is output. Frequency divider circuit 7
For example, divide this frequency by 2 and output the output signal 7. (Figure 5 f)
get.

Here, the synchronization protection circuit 5 receives its gate control signal 5. changes from high level to low level. As a result, the synchronization mismatch pulse 21 passes through the gate 4 and is input to the OR circuit 6 (FIG. 5C). When this and the reference clock pulse 3 are logically summed, the fifth
As shown in Figure e, the reference clock pulse is erased by one bit, and the signal 6. (Fig. 5e) is obtained. Divide the frequency of this signal (Fig. 5 f)
, a timing pulse shifted by one bit can be obtained from the frame counter 8. Note that when the frame counter 8 performs a 1-bit shift operation, that information is transmitted to the synchronization code detection circuit through the feedback line 9, and the timing for synchronization recovery is determined.

[Problem that the invention seeks to solve]

In such a device, the synchronization mismatch pulse is output with a width of exactly one period of the reference clock pulse, but
OR circuit 6 that calculates the logical sum of this and the reference clock pulse
For example, as shown in FIG. 6a1b, when the synchronization mismatch pulse 4I and the reference clock pulse 3 are input with phases shifted from each other, the output signal 61' (C in the same figure) is not shifted by one bit, resulting in a malfunction. It may occur.

When the frequency of the reference clock pulse is low, the probability of occurrence of such a malfunction is low, but as the frequency becomes high, malfunction becomes more likely to occur.

However, it is not easy to design a circuit to accurately match the phase of a high frequency signal, resulting in an increase in the cost of the device.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide a frame synchronization device that operates reliably even when the frequency of the reference clock pulse is relatively high.

[Means for solving problems]

The frame synchronization device of the present invention is provided in a transmission path for transmitting time-division multiplexed digital signals, and converts two or more groups of signal sequences included in the digital signal into frame synchronization pulses. A synchronization mismatch detection device that identifies and synchronizes by detection, which accepts the reference clock pulse that timings the operation of the device and the digital signal, and outputs a synchronization mismatch pulse when it detects a mismatch between the frame synchronization pulses. a frequency dividing circuit that divides the frequency of the reference clock pulse, and a synthesis circuit that receives the frequency-divided reference clock pulse and the synchronization mismatch pulse, compares and synthesizes the two, and outputs a synthesized signal shifted by 1 bit. and a frame counter that receives this composite signal and outputs a timing pulse for processing the digital signal.

Here, the synchronization mismatch detection section includes a synchronization code detection circuit that creates the synchronization mismatch pulse, a gate inserted in a line for transmitting this synchronization mismatch pulse to a synthesis circuit, and a synchronization mismatch pulse that is detected by a predetermined number of points. It consists of a synchronization protection circuit that opens the gate only when the synchronization has occurred a number of times in succession, and the synthesis circuit shifts the reference clock pulse whose frequency has been divided by two by the frequency dividing circuit by one bit at the timing when the synchronization mismatch pulse is input. Preferably, the combined signal is obtained by

[Effect]

As described above, in the frame synchronization device of the present invention, the reference clock pulse that controls the operation of the synchronization mismatch detection section, etc. is converted to a lower frequency using a frequency dividing circuit, and then compared and synthesized with the synchronization mismatch pulse. Therefore, compared to the case where a high frequency reference clock pulse and a synchronization mismatch pulse are directly compared and synthesized, there is no need to strictly consider the phase shift between the two.

This facilitates the circuit design of the frame synchronizer and improves the reliability of the circuit.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the frame synchronization device of the present invention.

This device includes a synchronization mismatch detection 1s10 and a frequency dividing circuit 16.
, a combining circuit 17 , and a frame counter 18 .

The synchronization mismatch detection section 10 is composed of a synchronization code detection circuit 2, a synchronization protection circuit 5, and a NOR gate 4, and converts the digital signal transmitted through the transmission line 1 to the branch line 1. This is a device that outputs a synchronization mismatch pulse of 2°.
This circuit performs the same operation as the corresponding circuit explained using the figures. The detailed configuration and operation of each of the synchronization code circuit detection 2, synchronization protection circuit 5, and NOR gate 4 are as follows.
゛The explanation is redundant with the explanation given in Fig. 4, so it will be omitted.

Further, the frequency dividing circuit 16 is a circuit that divides the frequency of the reference clock pulse 3 by two. Furthermore, as shown in FIG.
output signal 16. Or gate 17° that accepts and. and an inverter 17□ that inverts the signal.

The frame counter 18 receives the output signal 17. of the synthesis circuit 17. is further divided into a timing pulse 8. which is similar to that previously explained with reference to FIG. This is a circuit that outputs ~84.

Note that since the input signal suitable for the operation of this frame counter has a polarity opposite to that shown in FIG. 5f, the inverter 170 . is inserted.

FIG. 3 is a time chart illustrating the operation of the apparatus of the embodiment shown in FIG. 1 of the present invention.

In this time chart, the operation before time T is the fifth
This is the same as explained in the figure.

Here, the synchronization mismatch pulse 2, (3rd Z a
) When the signal is continuously output a certain number of times, the output 5. of the synchronization protection circuit 5 (Fig. 1) is output. (Figure 3 b) is from high level
'Changes to low level. As a result, the synchronization mismatch pulse 2I passes through the NOR gate 4 (1V!J) (FIG. 3C) to the OR gate 17° of the synthesis circuit 17.

(Figure 2). The reference clock pulse 3 (FIG. 3 d) is frequency-divided by the frequency divider circuit 16 and outputs 1
7oo (Figure 3e).

In FIG. 1, the output signal 4° of the NOR gate 4 and the output signal 161 of the frequency dividing circuit 16 are the 2nd vl! OR circuit 17 shown in J. , and a signal 17° (f in the same figure), which is shifted by 1 bit, is obtained. This is inverter 17
．． 1, the signal is inverted into a composite signal, and is input to a frame counter.

In this way, once the reference clock pulse is input to the frequency dividing circuit 1,
By dividing the frequency at 6 and lowering the frequency to 1/2, and then comparing and synthesizing it with the synchronous mismatched pulse, it is easy to match the phases of both signals, and it is possible to reliably achieve 1/2 without making any special modifications to the circuit. A bit-shifted signal can be obtained.

[Modified example]

The frame synchronization device of the present invention is not limited to the above embodiments.

The synchronization mismatch pulse output from the synchronization mismatch detection section is
Although an example has been shown in which the width corresponds to the period of the reference clock pulse, for example, if a frequency dividing circuit is added here to lengthen the pulse width, processing in the synthesis circuit can be further facilitated. Of course, the frequency of the reference clock pulse may also be divided accordingly, for example, by dividing the frequency by 4 and then inputting it to the synthesis circuit.

This synthesis circuit may have any configuration as long as it erases one bit of the frequency-divided reference clock pulse using a synchronization mismatch pulse, and can be modified by combining various known devices. be.

Furthermore, the circuit that uses the 1-bit shifted signal can be replaced not only with the frame counter shown in the embodiment but also with various other signal processing circuits.

〔Effect of the invention〕

The frame synchronizer of the present invention described above divides the frequency of the reference clock pulse using a frequency dividing circuit and then compares and synthesizes it with the synchronization mismatched pulse, so it can be used even when the reference clock pulse has a relatively high frequency. , it is possible to reliably obtain a signal shifted by one bit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the frame synchronization device of the present invention, and FIG. 2 is a wiring diagram showing an embodiment of the synthesis circuit.
Fig. 3 is a time chart showing its operation, Fig. 4 is a block diagram showing an example of a conventional frame synchronization device, Fig. 5 is a time chart showing its operation, and Fig. 6 is a time chart showing another operation thereof. It is. l...Transmission line, 2...Synchronization code detection circuit, 2...Synchronization mismatch pulse, 3...Reference clock pulse, 5... ... Synchronization protection circuit, 4 ... NOR circuit, 16 ... Frequency division circuit, 17 ... Synthesis circuit, 18 ... Frame counter. 1st Figure 2

Claims (1)

[Claims] 1. Provided in a transmission path for transmitting time-division multiplexed digital signals, two or more groups of signal strings included in this digital signal are converted into frames included in this signal string by frame synchronization pulses. A synchronization mismatch detection device that identifies and synchronizes by detection, which accepts a reference clock pulse for timing the operation of the device and the digital signal, and outputs a synchronization mismatch pulse when a mismatch between the frame synchronization pulses is detected. a frequency dividing circuit that divides the frequency of the reference clock pulse, and a synthesis circuit that receives the frequency-divided reference clock pulse and the synchronization mismatch pulse, compares and synthesizes the two, and outputs a synthesized signal shifted by 1 bit. and a frame counter that receives the composite signal and outputs a timing pulse for processing the digital signal. 2. The synchronization mismatch detection section includes a synchronization code detection circuit that creates the synchronization mismatch pulse, a gate inserted in a line for transmitting the synchronization mismatch pulse to a synthesis circuit, and a synchronization mismatch pulse that detects the synchronization mismatch pulse a predetermined number of times. and a synchronization protection circuit that opens the gate only when consecutive occurrences occur, and the synthesis circuit shifts the reference clock pulse whose frequency has been divided by two by the frequency dividing circuit by one bit at the timing at which the synchronization mismatch pulse is input. 2. The frame synchronization device according to claim 1, wherein the synthesized signal is obtained by