JPS62102666A - Blanking circuit - Google Patents

Abstract

PURPOSE:To attain very stable blanking by a simple circuit by mixing a vertical blanking pulse and a vertical synchronizing signal so as to form a blanking pulse thereby quickening the start time of the blanking pulse. CONSTITUTION:A vertical blanking pulse at a point A, a vertical synchronizing signal at a point C and a horizontal blanking pulse at a point D are fed to a base of a transistor (TR) 2 via a resistor R1, a diode D1, a resistor R3, a diode D3, a resistor R2 and a diode D2, the mixed waveform is shaped and a signal at the point B is outputted to a collector of the TR2. The vertical synchronizing signal C is added to the conventional vertical blanking pulse A to quicken the start timing of the blanking output pulse B by nearly 2H and very stable blanking is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a blanking circuit for television receivers, display monitors, and the like.

[Conventional technology]

FIG. 3 shows a specific example of a mixing and waveform shaping circuit for blanking signals for a display monitor.

The operation shown in FIG. 3 will be explained. Matsushita Electronics Industry AN5
Pin ■ of 521 vertical deflection output IC (1) is GND 1
■ is the output terminal, ■ is the output power supply, ■ is the input terminal, ■ is the retrace start pulse input terminal, ■ is the retrace pulse amplification output terminal,
■ is VCC, the signal input to the ■ bin is output from the bin to the deflection yoke (D, Y), and the vertical blanking pulse output from the bin passes through R1 and Dl and is applied through R2 and D2. It mixes the horizontal blanking pulse with the base of TR (2), shapes the waveform, and outputs it to the 0 point. Here, the vertical oscillation output pulse obtained in synchronization with the vertical synchronization signal is input to the ■ pin. Also, in Figure 4, 00 of Figure 3
The waveform and timing of the points are shown, ■ is the vertical scanning period, and H is the horizontal scanning period.

[Problem that the invention seeks to solve]

On screens that are overscanned in television receivers, etc., vertical retrace lines can be sufficiently eliminated using the groove-bottomed circuit as described above, but in display monitors, etc., there are many cases in which underscanning is used. Also, the bright control often causes the pack rasp to float. At that time, the delay in the start time of the vertical blanking pulse, which had not been a problem in the past, occurred at the bottom of the screen from 1 to
There was a problem in that it appeared as two bright lines.

In Figure 5, (3) is the pack cluster, and (4) is the video.

(5) is a vertical return line.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a blanking circuit that can reliably cancel vertical blanking lines with a simple circuit configuration.

[Means for solving problems]

This invention constructs a blanking circuit using a vertical synchronizing signal.

[Effect]

That is, the blanking circuit of the present invention mixes a conventional vertical blanking pulse and a vertical synchronization signal to create a blanking pulse and advances the start time of the blanking pulse.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

The 0-point vertical blanking pulse, the 0-point vertical synchronization signal, and the 0-point horizontal blanking pulse are R1°Dl, R8, D, respectively.
8, R2, and D2, apply to the base of TR (2), shape the mixed waveform, and output nine points of signals to the collector of TR (2).

Two vertical blanking signals (vertical blanking pulses).

FIG. 2 shows the timing of the vertical synchronization signal) and the blanking output pulse (0 point). As shown in the figure, in this invention,
By adding the vertical synchronization signal ■ to the conventional vertical blanking pulse ■, the start timing of the blanking output pulse ■ is about 2H earlier, and the blanking line (5) shown in Figure 5 can be erased. It is something to do.

〔Effect of the invention〕

As described above, according to the present invention, since the vertical synchronization signal is utilized, it is possible to perform extremely stable blanking with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a blanking circuit according to an embodiment of the present invention, FIG. 2 is a timing chart explaining signal waveforms of the circuit in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing an erasing circuit, FIG. 4 is a timing chart showing a conventional vertical blanking pulse, and FIG. 5 is a configuration diagram showing a screen of a display monitor. In the figure, (1) is the vertical output IC. (2) is a transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In a circuit for erasing vertical blanking during vertical blanking using a vertical blanking pulse synchronized with a vertical synchronizing signal indicating vertical scanning of a video signal, means for superimposing the vertical blanking signal on the vertical blanking pulse. A blanking circuit that uses this superimposed signal to cancel a vertical blanking line.