KR950022839A

KR950022839A - Character display on high definition television

Info

Publication number: KR950022839A
Application number: KR1019930030559A
Authority: KR
Inventors: 송진욱
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1993-12-29
Filing date: 1993-12-29
Publication date: 1995-07-28

Abstract

본 발명은 고화질 텔레비젼에서의 문자 표시장치로서 고화질 텔레비젼에 입력되는 비트 데이타를 이용하여 원하는 위치에, 원하는 문자를 표시하는 장치이다.The present invention is a device for displaying a desired character at a desired position by using bit data input to the high definition television as a character display device in a high definition television.

일반적으로 텔레비젼에서의 문자 표시는 방송국에서 발사하는 진폭변조(AM)전송파에 의한 아날로그신호를 이용하여 문자를 표시하고, 국제 텔레비젼 시스템 위원회(NTSC)방식에 의한 일반적 텔레비젼 방식이 사용되는 것으로 고화질 텔레비젼에서는 사용이 불가능한 것이다.In general, character display on television displays characters using an analog signal by an amplitude modulation (AM) transmission wave emitted by a broadcasting station, and a general television system by the National Television System Committee (NTSC) is used. It is not available in.

본 발명은 이러한 점을 감안하여 고화질 텔레비젼에 입력되는 비트 데이타를 이용하여 원하는 위치에, 원하는 문자를 표시하도록 한 것을 특징으로 한다.In view of the above, the present invention is characterized in that a desired character is displayed at a desired position by using bit data input to a high definition television.

Description

Character display on high definition television.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 문자 표시 처리기의 내부 구성도,1 is an internal configuration diagram of a character display processor;

제2도는 입력 데이타, 클럭, 그리고 스트로브의 관계를 나타낸 타이밍 다이아그램,2 is a timing diagram showing a relationship between input data, a clock, and a strobe,

제3도는 입력 데이타의 예를 도시한 것이다.3 shows an example of input data.

Claims

A data interface device 1 for interfacing the strobe signal, the clock signal, and the data signal with the decoder; A decoder (2) which detects address data in the input signal and sends it to the address multiplexer (3) and sends data bounded by a certain bit to the data memory (4); The decoder 2 accepts the address data, the central processor 8 receives the refresh address, and during the refresh operation sends the refresh address sent by the central processor 8 to the data memory 4, and otherwise separates the decoder 2 from the decoder 2. An address multiplexer 3 for sending address data; A data memory 4 for sending character data bounded by a certain bit to the character generator memory 5; A character generator memory 5 for generating characters by the data using character data bounded by a certain bit sent from the data memory 4; A shift register 6 which sends characters generated in the character generator memory 5 to the display output controller 7; A display output controller (7) for outputting each signal (R, G, B, BLK) to display characters transmitted through the shift register (6) using data bounded by fixed bits input from the data memory; A central processor (8) which receives the vertical synchronizing signal and the horizontal synchronizing signal, supplies a refresh address to the address multiplexer (3), and controls the display output controller (7) and the shift register (6); Character display device comprising a central processor (8) and an oscillator (9) connected to a horizontal synchronization signal to generate a clock.

※ Note: The disclosure is based on the initial application.