KR940006668Y1 - Processing circuit of width of character - Google Patents

Abstract

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Description

Image Character Width Control System

1 is a block diagram of the present invention image character width control system.

2 is an output waveform diagram of each part of FIG. 1;

3 is a screen state when dot stretch on / off according to FIG.

* Explanation of symbols for main parts of the drawings

1: shift register part 2: AND gate

3: dot delay unit 4: character data synthesis unit

TR1, TR2: Transistors R1-R4: Resistance

The present invention relates to image character width control of a low image bandwidth monitor, and more specifically, to adjust the width of the character generated by the character font generator at the user's discretion to display the character more clearly when used in the white background mode. A video character width control system for displaying.

In general, the image text is generated by the text font generator and displayed on the screen of the monitor through the image processor along with the color signal and the on-screen display signal.

However, since the width of the video text generated by the text font generator is fixed to a certain size and displayed on the screen, the video text generated by the text font generator is blurred on the screen when used in the white background mode of the monitor. There was a problem.

Therefore, the purpose of the present invention is to delay the image character by one bit by logical combination of the image character and the character width control signal according to the user's needs, and synthesize the original image character generated by the delayed image character and the character font generator. It is to provide a video character width control system to display the screen after adjusting the width.

The object of the present invention is a shift register unit for converting image character data inputted in parallel from the character font generation unit into serial data in synchronization with an input dot clock, and character data sequentially output from the shift register unit. An AND gate for ANDing and outputting a character width control signal input by a user's selection, a dot delay unit for delaying and outputting character data output from the AND gate by one dot, and a character delayed through the dot delay unit A character data synthesizing unit for synthesizing and outputting original character data through the data and shift register unit, and achieved by the following, will be described in detail with reference to the accompanying drawings of the present invention.

FIG. 1 is a block diagram of an image character width control system of the present invention, as shown in FIG. 1, an image dot data input in parallel from a character font generator (not shown) through a video input terminal VIN A shift register section 1 for sequentially converting and outputting serial data in synchronization with the clock DCLK, and character data being sequentially converted and output from the shift register section 1, and the character width adjusting terminal CWIN according to the user's selection. An AND gate 2 for outputting and outputting a character width adjustment signal inputted through the dot, a dot delay unit 3 for delaying and outputting character data output from the AND gate 2 by one dot, and the dot And a character data synthesizing unit 4 for synthesizing and outputting the character data delayed through the delay unit 3 and the original character data through the shift register unit 1.

In the above, the character data synthesizing section 4 connects the output of the shift register section 1 and the output of the dot delay section 3 to the bases of the transistors TR1 and TR2, respectively, and the respective resistors R1 ( Commonly connected to the collector and power supply terminals Vcc of the transistors TR1 and TR2 through R2, and emitters of the transistors TR1 and TR2 are connected to the video output terminal VDOUT through common connections. Configure the connection.

As another embodiment of the character data synthesizing unit 4 described above, an orifice for arranging the output of the shift register unit 1 and the output of the dot delay unit 3 is constructed.

When described in detail with reference to Figures 2 and 3 the operation, effects of the present invention configured as described above.

When 8-bit image character data is input in parallel from the character font generator through the video input terminal VIN, the shift register unit 1 synchronizes the input 8-bit parallel image character data with the input dot clock DCLK. Will output serial data. That is, as an example, when image characters are input in parallel from the character font generator as "10011000", the shift register unit 1 synchronizes the input image character data with the dot clock DCLK input as shown in FIG. As shown in FIG. 2B, serial image character data of "10011000" is sequentially output to one terminal of the AND gate 2 and the character data synthesizing unit 4. FIG. At this time, if the character width control signal as shown in FIG. 2C is input to the other terminal of the AND gate 2 in the high state by the user's selection by the character width control terminal CWIN, the AND gate 2 may have the input 8 bit. The character width control signal, such as the serial character data and the second c, is inputted to the dot delay unit 3 by ANDing as shown in FIG. 2d, and the dot delay unit C is a dot having the input character data as shown in the second e diagram. The output will be delayed. That is, when the original image character data of the character width adjustment signal and the shifted shift unit 1 that is ANDed through the AND gate 2 is input to the dot delay unit 3 as "10011000", the dot delay unit 3 The input data is delayed by one dot and output as "01001100" as shown in FIG. 2E, and inputted to the character data synthesizing section 4. Therefore, the character data synthesizing section 4 displays the original character data output from the shift register section 1 as shown in FIG. 2a and the character data delayed through the dot delay section 3 as shown in FIG. 11011100 "and display it on the screen as shown in FIG. 3b through the video output terminal (VDOUT). That is, the transistors TR1 and TR2 of the character data synthesizing unit 4 are turned on when the clock pulses output from the shift register unit 1 and the dot delay unit 3 are high (H) and are turned low. Since the voltage is turned off in the L state, the voltage of the power supply terminal Vcc is equal to the second f through the resistors R3 and R4 at the same clock pulses as the second and second e through the transistors TR1 and TR2. After being synthesized, the video output terminal VDOUT is displayed on the screen as shown in FIG. 3b to obtain a character figure in which the character width is adjusted.

On the other hand, when there is no character width adjustment signal by the user, that is, when the low signal is input to one terminal of the AND gate 2 through the character width adjustment terminal CWIN, the AND gate 2 is low regardless of the other input. By outputting a signal, a low signal is also output from the dot delay unit 3, thereby keeping the transistor TR2 of the character data synthesizing unit 4 off. Therefore, only the original image text data output from the shift register unit 1 is transmitted through the transistor unit TR1, the resistor R3, and the video output terminal VDOUT of the character data synthesizing unit 4 as shown in FIG. 3A. It will appear on the screen without adjusting the width.

In the case where the character data synthesizing unit 4 is replaced with an oragate, the same effect as described above may be obtained. That is, when the character data as shown in FIG. 2b of the shift register unit 1 is output and the character data as shown in FIG. 2e is output from the dot delay unit 3, the oragate displays the two inputs as shown in FIG. , As shown in FIG. 3B, a character figure in which the character width is adjusted can be obtained.

In this case, the parallel image text data is generated by the character font generator and immediately before being displayed on the screen. A value of "1" indicates dots on the screen, and a value of "0" does not directly dot on the screen. Since the value of "10011000" is combined with the delayed value "01001100", only the stroke of a certain character is displayed horizontally, and the width of the character can be adjusted without any problem. Such a function is built into the CRT control chip. It is commonly used as dot stretch, and when the width control input is "1", it is normally used for English terminal with dot stretch on state and when it is "0", it is used for Korean and Chinese characters terminal with dot stretch off state. use.

As described in detail above, the present invention is more effective for a low image bandwidth monitor because the minimum active pixel becomes two dot clocks, and by increasing only the horizontal width of the generated character, the generated character is used when used in the white background mode. There is a clearer effect.

Claims (2)

A shift register section 1 for converting parallel input image character text data into serial data in synchronization with an input dot clock DCLK, and the character data and the user's character data that are sequentially converted from the shift register section 1 and output. An AND gate 2 for activating and outputting the character width adjustment signal input by selection, a dot delay unit 3 for delaying and outputting the character data output from the AND gate 2 by one dot, and And a character data synthesizing unit (4) for synthesizing and outputting the character data delayed through the dot delay unit (3) and the original character data through the shift register unit (1). The character data synthesizing section 4 connects the output of the shift register section 1 and the output of the dot delay section 3 to the bases of the transistors TR1 and TR2, respectively, and the respective resistors. Commonly connected to the collector and power supply terminal Vcc of the transistors TR1 and TR2 through R1 and R2, and the emitters of the transistors TR1 and TR2 are connected via respective resistors R3 and R4. Image character width control system characterized in that the configuration by common connection.