JPH0595493A - Vertical blanking line erasing circuit - Google Patents

Abstract

PURPOSE:To surely erase a vertical blanking line for all raster periods by using a vertical pulse and a vertical synchronizing signal from a vertical deflection output amplifier to extend a tail end line and a front leading edge of a blanking line erasure signal. CONSTITUTION:A vertical pulse from a vertical deflection output amplifier is inputted to circuits 1-5, they obtain part of a blanking line erasure signal specifying a tail end edge of the blanking line erasure signal. Moreover, a vertical synchronizing signal whose phase is led more than the phase of a leading of a vertical flyback pulse is inputted, circuits 30-39 obtain part of a blanking line erasure signal specifying the front leading edge. Then the two signals are synthesized by a synthesis circuit 6, and a transistor (TR) 8 is used to convert the impedance and the result is fed to a video amplifier or a G1 of a CRT to implement blanking line erasure. Thus, the vertical blanking line is surely erased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical blanking circuit in a television receiver, a display monitor or the like.

[0002]

2. Description of the Related Art In a television receiver or a CRT display using a cathode ray tube (hereinafter referred to as CRT), if a blanking signal is not added to the CRT, a retrace line occurs on the sweep raster during the flyback period of the deflection current. Since it is unsightly, it is common to add a blanking signal to the CRT to prevent blanking. Especially in the case of a display monitor that is often displayed by underscan, even if there is a very slight retrace line at the top and bottom edges of the raster, it is not preferable because it is visible, and the retrace line is completely erased. There is a need.

A conventional vertical blanking circuit will be described below with reference to the drawings. FIG. 4 shows a conventional vertical blanking circuit. Reference numeral 1 denotes an input end of a vertical flyback pulse from a vertical deflection output circuit (not shown), and the vertical flyback pulse input here is applied to each of the first and second amplifier circuits 21 and 22. ..

In the first amplifying circuit 21, the vertical pulse passes through the resistor 2 and then is integrated by the capacitor 3 in the required amount, divided by the resistors 4 and 5 and applied to the base of the transistor 6 to be pulse-amplified. It Reference numeral 7 is a collector resistance common to the transistors 6 and 18, and reference numeral 8 is a transistor for forming an emitter follower together with the emitter resistance 9 for impedance conversion. 10 is resistance, 11
Is a coupling capacitor, and 12 is an output terminal. The amplifier circuit 21 acts to widen the trailing edge of the blanking pulse by the integration effect of the capacitor 3 of the input circuit.
In addition to the central part of the screen, the blanking of the upper part of the screen can be surely erased.

On the other hand, the vertical flyback pulse input to the second amplifier circuit 22 passes through the resistor 13, is differentiated by the capacitor 15, is applied to the base of the transistor 18, and is inverted and amplified. The resistor 14 is for adjusting the waveform of the input pulse. Reference numeral 17 is a bias resistor at the base of the transistor 18, and 16 is a diode for clipping the negative direction component of the input pulse. In the amplifier circuit 22, the phase of the input vertical flyback pulse advances due to the differential effect of the capacitor 15 and acts so as to widen the leading edge of the blanking pulse, so that the blanking line at the bottom of the screen can be erased in particular. Is configured.

The collectors of the transistors 6 and 18, which are the output points of the blanking pulse amplification circuits 21 and 22, are connected to the terminal 1 respectively.
Commonly connected at 9, the two blanking pulses are combined here. This combined negative polarity blanking pulse is impedance-converted by an emitter follower composed of a transistor 8 and a resistor 9, and then applied to G1 of a CRT through a resistor 10 and a coupling capacitor 11 for the period C
The RT is cut off, and the blanking operation is performed.

[0007]

However, in the above-mentioned prior art, since the trailing edge of the blanking pulse can be relatively easily widened by the integrating circuit, the vertical blanking line above the raster can be erased. However, the expansion of the leading edge of the vertical retrace pulse is limited by the phase shift due to the differentiation of the input pulse, and due to the difference in the vertical deflection circuit, the difference in the vertical cycle, etc., from the leading edge of the sync signal to the rising edge of the vertical flyback pulse. There may be a slight difference in time, and the width of the vertical blanking pulse in the leading edge direction may be insufficient to completely clear the blanking line at the bottom of the raster.

An object of the present invention is to provide a vertical blanking circuit capable of reliably blanking the blanking line in consideration of the problems of the conventional blanking line blanking technique.

[0009]

According to the present invention, a vertical pulse from a vertical deflection output amplifier is amplified, a waveform is shaped, etc., and a blanking signal is added to a video amplifier or a G1 electrode of a CRT, and a blanking period is added. In a vertical blanking circuit that cuts off the CRT during a period to cancel a vertical blanking line, a vertical pulse obtained from a vertical deflection output amplifier is input to define a trailing edge of the blanking signal. A first circuit for obtaining a part of an erase signal, a second circuit for inputting a vertical synchronizing signal to obtain a part of a blanking signal for defining a leading edge portion of the blanking signal, the first circuit, and It is a vertical blanking circuit having a combining circuit for combining output signals from the second circuit.

[0010]

According to the vertical blanking circuit of the present invention, in order to widen the leading edge of the vertical blanking pulse, the vertical synchronizing signal which always rises in advance of the phase of the rising edge of the vertical flyback pulse is blanked. Since it is used as part of the signal, a blanking signal with a sufficiently wide leading edge can be obtained. Therefore, the vertical blanking line can be surely erased regardless of the difference in the vertical deflection circuit, the vertical cycle, the timing of the video input signal, and the like.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a blanking circuit according to an embodiment of the present invention. In the figure, the same or corresponding portions as those of the conventional circuit of FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

Reference numeral 25 is a diode, 30 is a vertical synchronizing signal input terminal, 31, 32, 33 and 34 are resistors, and 35 and 36.
Is a capacitor, 37 is a transistor, and 38 is a diode. The vertical flyback pulse input terminal 1 is shown in FIG.
Vertical deflection output amplifier (not shown) as shown in FIG.
The vertical flyback pulse from is applied to the base of the grounded-emitter transistor 6 via the coupling resistor 4 and the diode 25 after being subjected to appropriate integration by the integrating circuit composed of the resistor 2 and the capacitor 3. An inverted and amplified output appears at the collector 19 of the transistor 6. These means constitute the first circuit.

On the other hand, a negative vertical synchronizing pulse as shown in FIG. 2A is applied to the terminal 30, and the vertical synchronizing pulse is a delay circuit composed of a resistor 31 and a capacitor 35 of a relatively small capacity. After some delay, capacitor 3
An output that is applied to the base of a PNP transistor 37 having a grounded emitter through 6 and is inverted and amplified appears at the collector 39 of this transistor 37. The inverted and amplified vertical synchronizing signal passes through the coupling resistor 34 and the diode 34 (these means constitute a second circuit), and the transistor 6
Similarly, these two pulses are combined (combining circuit), inverted and amplified by the transistor 6, and then impedance-converted by the emitter follower composed of the transistor 8 and the resistor 9, and the resistor 10 and the coupling capacitor 11 are connected. After that, it is output as a vertical blanking pulse to the terminal 18 and applied to G1 (not shown) of the CRT to perform a blanking operation. The capacitor 35 for delaying the vertical synchronizing signal is not always necessary.

A more detailed description will be given with reference to the waveform diagram of FIG. The figure (a) shows the waveform of the vertical synchronizing signal applied to the terminal 30, and the figure (b) shows the waveform of the vertical flyback pulse applied to the terminal 1. The rising of this vertical flyback pulse is generally. There is a slight delay from the rising edge of the vertical synchronizing signal. The same figure (c) shows a resistor 4,
An output waveform is shown when only the vertical flyback pulse applied to the base of the transistor 6 through the diode 25 is inverted and amplified by the transistor 6 (when the vertical synchronizing signal is not input to the terminal 30). The trailing edge of the waveform c is wider than the waveform b by the action of the integrating circuit consisting of. FIG. 6D shows a waveform at the collector 39 obtained by inverting and amplifying the negative vertical synchronizing signal applied to the terminal 30 by the transistor 37. This waveform d
Is slightly delayed from the input waveform a due to the action of the delay circuit including the resistor 31 and the capacitor 35. However, it is ahead of the waveform c. FIG. 8E shows a pulse for vertical blanking of the collector 19 after the vertical synchronizing signal and the vertical flyback pulse are combined at the base of the transistor 6 and inverted and amplified by the transistor 6. The leading edge of this pulse is equal to the leading edge of waveform d, which is equivalent to widening the leading edge of waveform c obtained by inverting and amplifying the apparent vertical flyback pulse. FIG. 6F shows the vertical deflection current waveform. The scanning line performs a blanking operation during the flyback period shown by the waveform b. During the blanking operation, if a blanking signal is added to the CRT and the CRT is not cut off, an oblique so-called vertical blanking line appears on the screen. appear. The retrace line of the upper part of the raster of this vertical retrace line corresponds to the trailing edge of the retrace line erasing pulse. It can be erased relatively easily by the integrating circuit of 3. The blanking line at the bottom of the raster corresponds to the leading edge of the blanking pulse,
As described above, by widening the leading edge of the blanking pulse by the vertical synchronizing signal applied to the terminal 30, the blanking can be surely erased.

FIG. 3 shows another embodiment, in which a positive vertical synchronizing signal is applied to the terminal 30 and the amplifying circuit 2 for the vertical synchronizing signal is used.
After pulse amplification at 2 ', its output is superimposed on the output of the amplifier circuit 21 at the terminal 19 to produce a vertical blanking signal as in the first embodiment.

In the amplifier circuit 22 ', the capacitor 35 and the resistor 32 are grounded in response to the positive vertical synchronizing signal, and the output applied to the terminal 19 is taken out from the emitter terminal of the transistor 37.

[0018]

As described above, the present invention inputs the vertical pulse obtained from the vertical deflection output amplifier and obtains a part of the blanking signal which defines the trailing edge of the blanking signal. And a second circuit for inputting a vertical synchronizing signal whose phase is ahead of the rising edge of the vertical flyback pulse to obtain a part of the blanking signal that defines the leading edge of the blanking signal,
Since the composite circuit for combining the output signals from the first circuit and the second circuit is provided, the vertical blanking on the raster can be reliably erased from the uppermost end to the lowermost end with an extremely simple and inexpensive circuit configuration. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a vertical blanking circuit according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of each part of the vertical blanking circuit.

FIG. 3 is a diagram of a vertical blanking circuit showing another embodiment of the present invention.

FIG. 4 is a diagram showing a conventional vertical blanking circuit.

[Description of symbols] 1 vertical flyback pulse input terminal 6 pulse amplification transistor 8 impedance conversion transistor 21 first vertical pulse amplification circuit 22 second vertical pulse amplification circuit 30 vertical synchronization signal input terminal 37 vertical Sync signal amplifying transistor 38 Vertical sync signal coupling diode

Claims (1)

[Claims] 1. A vertical pulse from a vertical deflection output amplifier is amplified, waveform shaped, and the like, and is applied to a video amplifier or a G1 electrode of a CRT as a blanking signal, and the CRT is cut off during a blanking period. A vertical blanking circuit for erasing a vertical blanking line receives a vertical pulse obtained from the vertical deflection output amplifier to obtain a part of the blanking signal which defines a trailing edge of the blanking signal. A first circuit and a second circuit for inputting a vertical synchronizing signal whose phase is ahead of the rising edge of the vertical flyback pulse to obtain a part of the blanking signal for defining the leading edge of the blanking signal. And the first
A vertical retrace line erasing circuit comprising a circuit and a synthesizing circuit for synthesizing output signals from the second circuit.