JPS5915154Y2 - Vertical blanking pulse forming circuit - Google Patents

Description

[Detailed description of the invention] In television broadcasting, various test signals, such as VIT signal and VIR signal, are added to the video signal to test transmission paths.
A test signal called a signal may be inserted.

In this case, the test signal is inserted at the end of the vertical blanking period, for example, at the 19th and 20th H, so as long as the size of the receiving screen is normal, this test signal will be outside the effective screen. Although they do not appear on the screen, even if the screen size is normal, when the electron beam of the picture tube is modulated by this test signal, secondary electron emission occurs outside the effective screen due to the scanning of the beam. This secondary electron emission causes the upper part of the screen to shine, which is undesirable.

In order to eliminate this inconvenience, it is sufficient to make the pulse width of the vertical blanking pulse sufficiently wide. However, the vertical blanking pulse is obtained from the vertical deflection circuit, and the vertical Since efficiency is better when the pulse width of the pulse is narrower, it is not possible to simply increase the pulse width of the vertical blanking pulse.

It is also possible to obtain a narrow pulse from the vertical deflection circuit and integrate it to create a wide vertical blanking pulse, but in this case, the phase of the vertical blanking pulse obtained would be delayed. After all, it is not possible to make the width sufficiently wide.

The present invention attempts to solve these problems with an extremely simple configuration.

Therefore, in the present invention, an integral pulse and a differential pulse are obtained from the vertical pulse, and these pulses are combined to obtain the desired vertical blanking pulse.
An example of this will be explained below.

In FIG. 1, 1 and 2 are video intensifiers, and 3 is a picture tube.
supplied to

Further, 4 indicates a vertical oscillation circuit, 5 indicates a vertical deflection output circuit,
6a and 6b are the output transistors, and these transistors 6a and 6b are connected in 5EPP, and the vertical deflection coil 8 and capacitor 9 are connected between the emitters of the transistors 6a and 6b, that is, the output terminal 7 of the circuit 5, and the ground. A series circuit is connected.

Then, the output pulse of the oscillation circuit 4 is supplied to the transistors 6a and 6b through the driving transistor 10, which turns the transistors 6a and 6b on and off alternately, and the emitter, that is, the output terminal 7, as shown in FIG. 2A. As is usual, the vertical deflection voltage Ea is extracted and supplied to the deflection coil 8 to perform vertical deflection.

In the present invention, the vertical deflection output terminal 7 is connected to one end of a DC cut capacitor 11, and the other end of this capacitor 11 is connected to the output terminal 14 through a series circuit consisting of two resistors 12 and 13. 12 and 13 are grounded through a capacitor 15, and resistors 12 and 1 are grounded through a capacitor 15.
A resistor 16 is connected in parallel to the series circuit of 3.

Note that 17 is a resistor connected between the output terminal 14 and ground.

In the embodiment shown in FIG. 1, a transistor 18 is provided whose base is connected to the output terminal 14 and whose emitter is connected to the resistor 19.
This is a case where the input terminal 21 of the horizontal pulse P is connected to the input terminal 21 of the horizontal pulse P through the resistor 20, and the collector is connected to the connection point between the amplifiers 1 and 2.

According to the above-mentioned configuration, an integrating circuit 22 is constituted by the resistors 12, 13 and the capacitor 15, and the signal obtained at the output terminal 7 (voltage Ea shown in FIG. 4A) is integrated in this integrating circuit 22. , is supplied to the output terminal 14.

On the other hand, a differentiating circuit 2 with a capacitor 11 and a resistor 16
3 is constructed, and the signal obtained at the output terminal 7 (voltage Ea shown in FIG. 4A) is differentiated by this differentiation circuit 23 and supplied to the output terminal 14.

In the above circuit, the voltage at the connection point between capacitor 11 and resistor 12 is Eb, the voltage at the connection point between resistors 12 and 13 is Ec, the voltage at output terminal 14 is Ed, and the voltage at the collector of transistor 18 is Ee. Then, these become as shown in FIG. 2 B, C, D, and E, respectively.

That is, the voltage Ea is differentiated by the differentiating circuit 23 and becomes
The voltage Eb becomes as shown in , and the voltage Ea becomes the voltage Eb as shown in the integrating circuit 22
The voltage Ec shown in FIG. 2C is integrated, and since these are added, the voltage iEd shown in the second diagram is obtained at the output terminal 14.

Furthermore, since this voltage Ed is supplied to the base of the transistor 18, the voltage Ee shown in FIG. 2E is obtained at its collector, and blanking is performed during the falling period τ.

In the example of FIG. 1, a horizontal pulse P for horizontal blanking is supplied to the emitter of the transistor 18, and this also performs a blanking operation, but the signal (voltage) based on this operation is It is omitted in Figure 2E.

According to the present invention, by increasing the time constant of the integrating circuit 22 and widening the pulse width of the pulse Ec, even if the phase of the pulse Ea is delayed, the rising portion of the pulse Ee is a differential pulse Eb, so that the pulse width is vertical. There is no delay in the start point of blanking.

As an example, if the values of the elements of the integrating circuit 22 and the differentiating circuit 23 are: resistors 12 and 13 22KQ capacitor 15 0.022μF capacitor 11 0.47μF resistor 16 68KJ7, the vertical The vertical blanking period could be set to 1.1 msec without delaying the start point of blanking.

According to the present invention, even if a test signal is inserted into the video signal, it can be blanked reliably.
The top of the image receiving screen does not shine.

In this case, there is no need to widen the pulse width of the vertical pulse in the vertical deflection circuit, so there is no reduction in efficiency.

In addition, in the present invention, capacitors 11 and 15, and resistor 12.1
The purpose can be achieved with a small number of parts (3 and 16), and the structure is very simple and inexpensive.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an example of the present invention, and FIG. 2 is a waveform diagram for explaining the same. 3 is a picture tube, 4 is a vertical oscillation circuit, 5 is a vertical deflection output circuit, 8 is a vertical deflection coil, 11.15 is a capacitor, respectively.
12, 13, and 16 are resistors.

Claims (1)

[Scope of utility model registration request] The output end of the vertical deflection output circuit of the television receiver is connected to one end of a DC cut capacitor, and the other end of the capacitor is connected to the output terminal through a series circuit consisting of two resistors. The connection point of the resistor is grounded through a capacitor, and one resistor is connected in parallel to the series circuit consisting of the two resistors so that a vertical blanking pulse is obtained from the output terminal. A vertical blanking pulse forming circuit is inserted at the end of the ranking period to eliminate harmful effects on the receiver side caused by test signals, etc.