JPS6199370A - Manufacture of solid-state image sensor element - Google Patents
Manufacture of solid-state image sensor elementInfo
- Publication number
- JPS6199370A JPS6199370A JP59220547A JP22054784A JPS6199370A JP S6199370 A JPS6199370 A JP S6199370A JP 59220547 A JP59220547 A JP 59220547A JP 22054784 A JP22054784 A JP 22054784A JP S6199370 A JPS6199370 A JP S6199370A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- transparent electrode
- pixels
- film
- photoconductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000926 separation method Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000003384 imaging method Methods 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 2
- 206010047571 Visual impairment Diseases 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000003949 trap density measurement Methods 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、半導体基板上に走査回路および光導電膜を積
層化した固体撮像素子の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a solid-state imaging device in which a scanning circuit and a photoconductive film are laminated on a semiconductor substrate.
従来技術と問題点
この種の積層型の固体撮像素子においては、光感度を高
めるために、非晶質シリコンによる光導電膜をＭＯＳ型
、 、ＣＣＯ型あるいはＢＢＤ型の走査回路基板上に積
層させている。この場合、積層される非晶質シリコンの
うち、走査回路基板上の電極端やコンタクトホール部な
どの段差部にボイドやクラックなどの欠陥が発生しやす
い。これら欠陥が光導電層の画素間分離後に残っている
と、その欠陥部分が選択的に、はやくエツチングされた
り、残存欠陥部分にリーク電流が流れて特性を著しく劣
化させる原因となる。Prior Art and Problems In this type of stacked solid-state imaging device, a photoconductive film made of amorphous silicon is stacked on a MOS, CCO, or BBD scanning circuit board in order to increase photosensitivity. ing. In this case, defects such as voids and cracks are likely to occur in stepped portions of the stacked amorphous silicon, such as electrode ends and contact hole portions on the scanning circuit board. If these defects remain after the photoconductive layer is separated between pixels, the defective portions may be selectively and quickly etched, or a leakage current may flow through the remaining defective portions, causing a significant deterioration of the characteristics.
さらにまた、非晶質シリコンを利用した固体撮像素子に
おいては、平面方向の抵抗が他の材料に比べて若干低い
ため、解像度が大きく劣化し、混色も大きい。この欠点
を除去すべく非晶質シリコン膜を高抵抗化した場合、キ
ャリア移動度が低下したり、トラップ密度の増加に伴な
う残像の増加などの欠点があった。Furthermore, in a solid-state imaging device using amorphous silicon, the resistance in the planar direction is slightly lower than that of other materials, so the resolution is significantly degraded and color mixture is large. If the amorphous silicon film is made to have a high resistance in order to eliminate this drawback, there are drawbacks such as a decrease in carrier mobility and an increase in afterimages due to an increase in trap density.
発明の目的
そこで、本発明の目的は、上述した解像度の劣化や混色
の発生という欠点を除去するために、非晶質シリコン膜
を画素毎に分離させると共に、その際にクラックやボイ
ドなどの欠陥が発生しないように適切に処理工程を進め
、しかも工程の簡略化を図った固体撮像；１８子の製造
方法を提供することにある。Purpose of the Invention Therefore, an object of the present invention is to separate the amorphous silicon film for each pixel and eliminate defects such as cracks and voids in order to eliminate the above-mentioned drawbacks such as deterioration of resolution and occurrence of color mixture. It is an object of the present invention to provide a method for manufacturing a solid-state imaging device, in which the processing steps are appropriately carried out so as not to occur, and the steps are simplified.
発明の構成
かかる目的を達成するために１本発明では、複数の画素
の走査回路を設けた半導体基板上に光導電膜および透明
電極層をこの順序で配置し、前記半導体基板上の複数の
電極と前記透明電極層とにより前記複数の画素を区画す
るようにした固体撮像素子を製造するにあたり、前記半
導体基板上を覆って前記複数の電極を構成するための電
極層を形成する工程と、前記電極層の上を覆って前記光
導電膜を形成する工程と、前記光導電膜の上を覆って第
１透明電極層を形成する工程と、前記第１透明電極層上
に、前記複数の画素に対応するレジストパターンを形成
する工程と、前記第１透明電極層および前記光導電膜を
前記レジストパターンによってエツチング処理して、こ
れら第１透明電極層および光導電膜の画素間を空間的に
分離する工程と、当該画素間の分離された第１透明電極
層および光導電膜の配置されている前記電極層を前記レ
ジストパターンによってエツチング処理し、当該電極層
を画素間で分離する工程とを具えたことを特徴する。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention includes a photoconductive film and a transparent electrode layer arranged in this order on a semiconductor substrate provided with a plurality of pixel scanning circuits, and a plurality of electrodes on the semiconductor substrate. and the transparent electrode layer to partition the plurality of pixels, a step of forming an electrode layer covering the semiconductor substrate to form the plurality of electrodes; forming the photoconductive film covering the electrode layer; forming a first transparent electrode layer covering the photoconductive film; and forming the plurality of pixels on the first transparent electrode layer. and etching the first transparent electrode layer and the photoconductive film using the resist pattern to spatially separate pixels of the first transparent electrode layer and the photoconductive film. and a step of etching the separated first transparent electrode layer between the pixels and the electrode layer on which the photoconductive film is arranged using the resist pattern to separate the electrode layer between the pixels. It is characterized by something.
本発明の第２の形態では、複数の画素の走査回路を設け
た半導体基板上に光導電膜および透明電極層をこの順序
で配置し、半導体基板上の複数の電極と透明電極層とに
より複数の画素を区画するようにした固体撮像素子を製
造するにあたり、半導体基板上を覆って複数の電極を構
成するための電極層を形成する工程と、電極層の上を覆
って光導電膜を形成する工程と、光導電膜の上を覆って
第１透明電極層を形成する工程と、第１透明電極層上に
、複数の画素に対応するレジストパターンを形成する工
程と、第１透明電極層および光導電ｎ々をレジストパタ
ーンによってエツチング処理して、これら第１透明電極
層および光導電膜の画素間を空間的に分離する工程と、
画素間の分離された第１透明電極層および光導電膜の配
置されている電極層をレジストパターンによってエツチ
ング処理し、電極層を画素間で分離する工程と、その分
離された画素間の部分をパッシベーション膜により覆う
工程と、第１透明電極層およびパッシベーション膜を覆
って第２透明電極層を被着する工程と、第２透明電極層
のうち画素間の分離部分に対応する部分に光シールド層
を配置する工程とを具えたことを特徴とする。In the second embodiment of the present invention, a photoconductive film and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a plurality of pixel scanning circuits, and a plurality of photoconductive films and a transparent electrode layer on the semiconductor substrate are arranged in a plurality of In manufacturing a solid-state imaging device that divides pixels, there are two steps: forming an electrode layer covering the semiconductor substrate to form a plurality of electrodes, and forming a photoconductive film over the electrode layer. a step of forming a first transparent electrode layer covering the photoconductive film; a step of forming a resist pattern corresponding to a plurality of pixels on the first transparent electrode layer; and a step of forming a first transparent electrode layer on the first transparent electrode layer. and a step of etching the photoconductive layers using a resist pattern to spatially separate the pixels of the first transparent electrode layer and the photoconductive film;
A step of etching the separated first transparent electrode layer between the pixels and the electrode layer on which the photoconductive film is arranged using a resist pattern to separate the electrode layer between the pixels, and a step of separating the electrode layer between the separated pixels. a step of covering with a passivation film, a step of depositing a second transparent electrode layer covering the first transparent electrode layer and the passivation film, and a step of applying a light shield layer to a portion of the second transparent electrode layer corresponding to the separation portion between pixels. The method is characterized by comprising a step of arranging the.
発明の実施例 以下に、図面を参照して、本発明の詳細な説明する。Examples of the invention The present invention will be described in detail below with reference to the drawings.
第１図（Ａ）〜（Ｄ）は本発明固体撮像素子の製造方法
の順次の工程の一例を示し、ここで、１００は走査回路
基板、２００は光導電膜部分を示す、走査回路基板１０
０は公知のい力１なる形態であってもよ“ 〈１例えば
、ＭＯＳ型素子、ｃｃｏあるいはＢＢＤで構成できる。FIGS. 1(A) to 1(D) show an example of the sequential steps of the method for manufacturing a solid-state image sensor of the present invention, in which 100 is a scanning circuit board, 200 is a photoconductive film portion, and a scanning circuit board 10
0 may be in the form of a well-known force 1. For example, 0 may be configured with a MOS type element, CCO, or BBD.
以下では、その−例として、ＭＯＳ型素子により走査回
路基板１００を構成して示す。In the following, as an example, the scanning circuit board 100 is constructed using MOS type elements.
すなわち、走査回路基板１００は、ソースｌ、ドレイン
２およびゲート３から成るＭＯＳ電界効果トランジスタ
を有し、各ＭＯＳ電界効果トランジスタ間を５ｉ０２絶
縁層４で分離する。ゲート３はＰＳＧ （リンシリケー
トガラス）あるいはＳｉＯ＋による絶縁層５に埋め込ま
れている。６はソース１に接続された電極であり、この
電極６をＰＳ（ｉ、 ５ｉ０２゜Ｓｉ３Ｎ４あるいはポ
リイミド等の有機物による絶縁層７により覆って、その
上に、ソースｌに接続され、後述する工程を経てから１
画素を区画する電極層８を一様に配置する。電極層８と
してはＡＪＩ −Ｓｉ 、 ＡｆＬ −５ｉ−Ｃ：ｕ
またはＭｏなどの遷移金属を用いることができる。That is, the scanning circuit board 100 has a MOS field effect transistor consisting of a source 1, a drain 2, and a gate 3, and each MOS field effect transistor is separated by a 5i02 insulating layer 4. The gate 3 is embedded in an insulating layer 5 made of PSG (phosphosilicate glass) or SiO+. Reference numeral 6 denotes an electrode connected to the source 1. This electrode 6 is covered with an insulating layer 7 made of an organic material such as PS (i, 5i02°Si3N4 or polyimide), and is connected to the source 1 on top of the insulating layer 7. After 1
Electrode layers 8 that partition pixels are uniformly arranged. As the electrode layer 8, AJI-Si, AfL-5i-C:u
Alternatively, a transition metal such as Mo can be used.
光導電ｎ！ｉｉ部分２００は、電極層８を下地電極とし
て、その上に形成される。下地電極８の上にまずノンド
ープのままのｎ形非晶質シリコン膜またはボロンを添加
した高抵抗のｉ形の非晶質シリコン膜９を配置し、この
ｎ形（ｉ形）非晶質シリコン膜９の上に不純物添加によ
るｐ十形非晶質シリコン膜１０を配置し、さらにこのｐ
＋形非晶質シリコンＩＩ！２１０の上にＩＴＯなどの第
１透明電極層１１を配置する。Photoconductive n! The ii portion 200 is formed on the electrode layer 8 using it as a base electrode. First, an undoped n-type amorphous silicon film or a boron-doped high-resistance i-type amorphous silicon film 9 is placed on the base electrode 8, and this n-type (i-type) amorphous silicon A p-type amorphous silicon film 10 doped with impurities is disposed on the film 9, and the p-type amorphous silicon film 10 is
+ type amorphous silicon II! A first transparent electrode layer 11 made of ITO or the like is placed on top of the layer 210 .
ついで、第１図（Ａ）に示すように、透明電極層ｌｌ上
に画素領域に対応してレジストパターン１２を形成して
からエツチングを行い、第１図（Ｂ）に示すように、ま
ず光導電膜部分２００に対して画素間の分離を行う、つ
いで、同じレジストパターンを用いて、下地電極８に対
するエツチングを行って第１図（Ｃ）に示すように、溝
１３を形成して、下地電極８の画素間の分離を行う、こ
のように、本発明では、光導電膜部分２００の画素分離
と、下地電極８の画素分離とを同一のエツチングマスク
を用いて行うので、レジストパターンを２回形成して除
去する工程を１回に減らすことができ、以て工程の簡略
化を図ることができると共に、セルフアライメントによ
ってパターンの合わせずれがない利点も生じる。Next, as shown in FIG. 1(A), a resist pattern 12 is formed on the transparent electrode layer 11 corresponding to the pixel area, and then etching is performed. The conductive film portion 200 is separated between pixels, and then, using the same resist pattern, the base electrode 8 is etched to form a groove 13 as shown in FIG. 1(C). In this way, in the present invention, the pixel separation of the photoconductive film portion 200 and the pixel separation of the base electrode 8 are performed using the same etching mask, so that the resist pattern can be divided into two. The number of forming and removing steps can be reduced to one, thereby simplifying the process, and also has the advantage that there is no misalignment of patterns due to self-alignment.
ついで、第１図（Ｄ）に示すように、溝１３に？溝分離
のパッシベーション膜１４トしてｐ形５ｉ３Ｎａ ＋！
ｌ；＋０２などの無機物やポリイミドなどの有機物をプ
ラズマＣｖ［］法などによって付着させる。Then, as shown in FIG. 1(D), the ? Passivation film 14 for trench isolation and p-type 5i3Na +!
An inorganic substance such as +02 or an organic substance such as polyimide is deposited by a plasma Cv[] method or the like.
さらに、ｉ明室極層１１およびこのパッジベージ冒ン膜
１４を覆って全面に第２の透明電極層１５を付着し、そ
の透明電極層１５のうち、画素間分離領域には金属によ
る光シールド層１６を被着する。Furthermore, a second transparent electrode layer 15 is attached to the entire surface covering the i-bright room electrode layer 11 and the padding film 14, and a metal light shield layer is formed in the pixel separation region of the transparent electrode layer 15. 16 is applied.
このようにして形成した固体撮像素子の表面は第２図に
示すようになる。The surface of the solid-state imaging device thus formed is as shown in FIG.
なお、上側では、光導電膜部分は、表面側から透明電極
層１１．１５−ｐ＋十形非晶質シリコン膜０−ｎ形（ｉ
形）非晶質シリコン膜９．が配置された構造としたが、
下地電極８とｎ形（ｉ形）非晶質シリコン膜９との間に
ｐ−形非晶買シリコン膜を配置したり、あるいはこれら
の構造のうち透明型Ｆｉ層を設けない構造としてもよい
。Incidentally, on the upper side, the photoconductive film portion includes transparent electrode layer 11.15-p+decade amorphous silicon film 0-n type (i
form) amorphous silicon film9. The structure is arranged in such a way that
A p-type amorphous silicon film may be disposed between the base electrode 8 and the n-type (i-type) amorphous silicon film 9, or a structure in which a transparent Fi layer is not provided among these structures may be used. .
発明の効果
以上から明らかなように、本発明によれば、画素間が完
全に分離されているので、解像度の劣化および混色の発
生を完全に防止でき、しかもかかる分離は、まず非晶質
シリコン膜を一様な下地電極上に付着してから行うので
、従来のように下１ 地電極の端にステップ部分
が形成されている場合に発生するボイドやクラッタなど
の欠陥を防止できる。いかもまた、非晶質シリコン膜の
分離および下地電極の分離を同一のレジストマスクを用
いてセルフアライメントの状態で行うことができるので
、マスクの合わせずれがなく、かつ工程の簡略化を図る
ことができる。Effects of the Invention As is clear from the above, according to the present invention, pixels are completely separated, so deterioration of resolution and occurrence of color mixture can be completely prevented. Since the film is applied after being deposited on a uniform base electrode, defects such as voids and clutter that occur when step portions are formed at the ends of the base electrode as in the conventional method can be prevented. Furthermore, since the separation of the amorphous silicon film and the underlying electrode can be performed in a self-aligned state using the same resist mask, there is no misalignment of the mask, and the process can be simplified. I can do it.
さらに加えて、本発明により形成された固体撮像素子は
、平面方向の抵抗が低くても移動度が大きく、かつトラ
ップ密度の小さい膜組成を利用できるので、短波長分光
感度が劣化せず、かつ、残像の少ない特性を得ることが
できる。さらにまた、光シールド層を金属層で形成する
ので、透明電極層の段差切れなどがなく、その信頼度を
高めるのに寄与する。In addition, the solid-state imaging device formed according to the present invention has high mobility even with low in-plane resistance, and can utilize a film composition with low trap density, so short wavelength spectral sensitivity does not deteriorate, and , characteristics with less afterimage can be obtained. Furthermore, since the light shield layer is formed of a metal layer, there is no step breakage in the transparent electrode layer, which contributes to increasing its reliability.
第１図（Ａ）〜（Ｄ）は本発明における一連の製造工程
を示す断面図、
第２図は本発明により形成された固体撮像素子の表面を
示す平面図である。
１・・・ソース、
２・・・ドレイン、
３・・・ゲート、
４・・・絶縁層。
５・・・絶縁層。
６・・・電極、
７・・・絶縁層、
８・・・下地電極、
９・・・ｎ （ｉ）形非晶質シリコン膜、ｌＯ・・・Ｐ
十形非晶質シリコン膜、
１１・・・第１透明電極層、
１２・・・レジストパターン、
１３・・・分離溝、
１４・・・パッシベーション膜、
１５・・・第２透明電極層、
１６・・・光シールド層。
手続補正書
昭和６０年１月８日
特許庁長官 志 賀 学 殿
１、事件の表示
特願昭５ｉ９−２２０５４７号 ２、発明の
名称
固体撮像素子の製造方法
３、補正をする者
事件、との関係 特許出願人
富士写真フィルム株式会社
４、代理人
６、補正の対象
明細書のｆ３、発明の詳細な説明」の欄７、補正の内容FIGS. 1A to 1D are cross-sectional views showing a series of manufacturing steps according to the present invention, and FIG. 2 is a plan view showing the surface of a solid-state image sensor formed according to the present invention. 1... Source, 2... Drain, 3... Gate, 4... Insulating layer. 5...Insulating layer. 6... Electrode, 7... Insulating layer, 8... Base electrode, 9... n (i) type amorphous silicon film, lO...P
Decamorphic amorphous silicon film, 11... First transparent electrode layer, 12... Resist pattern, 13... Separation groove, 14... Passivation film, 15... Second transparent electrode layer, 16 ...Light shield layer. Procedural amendment January 8, 1985 Manabu Shiga, Commissioner of the Japan Patent Office 1. Indication of the case, Patent Application No. 1987-220547 2. Name of the invention, Process for manufacturing solid-state image sensor 3. Person making the amendment, Related: Patent applicant Fuji Photo Film Co., Ltd. 4, agent 6, f3 of the specification subject to amendment, column 7 of ``Detailed explanation of the invention'', content of amendment
Claims (1)
電膜および透明電極層をこの順序で配置し、前記半導体
基板上の複数の電極と前記透明電極層とにより前記複数
の画素を区画するようにした固体撮像素子を製造するに
あたり、 前記半導体基板上を覆って前記複数の電極を構成するた
めの電極層を形成する工程と、 前記電極層の上を覆って前記光導電膜を形成する工程と
、 前記光導電膜の上を覆って第１透明電極層を形成する工
程と、 前記第１透明電極層上に、前記複数の画素に対応するレ
ジストパターンを形成する工程と、前記第１透明電極層
および前記光導電膜を前記レジストパターンによってエ
ッチング処理して、これら第１透明電極層および光導電
膜の画素間を空間的に分離する工程と、 当該画素間の分離された第１透明電極層および光導電膜
の配置されている前記電極層を前記レジストパターンに
よってエッチング処理し、当該電極層を画素間で分離す
る工程とを具えたことを特徴とする固体撮像素子の製造
方法。 ２）複数の画素の走査回路を設けた半導体基板上に光導
電膜および透明電極層をこの順序で配置し、前記半導体
基板上の複数の電極と前記透明電極層とにより前記複数
の画素を区画するようにした固体撮像素子を製造するに
あたり、 前記半導体基板上を覆って前記複数の電極を構成するた
めの電極層を形成する工程と、 前記電極層の上を覆って前記光導電膜を形成する工程と
、 前記光導電膜の上を覆って第１透明電極層を形成する工
程と、 前記第１透明電極層上に、前記複数の画素に対応するレ
ジストパターンを形成する工程と、前記第１透明電極層
および前記光導電膜を前記レジストパターンによってエ
ッチング処理して、これら第１透明電極層および光導電
膜の画素間を空間的に分離する工程と、 当該画素間の分離された第１透明電極層および光導電膜
の配置されている前記電極層を前記レジストパターンに
よってエッチング処理し、当該電極層を画素間で分離す
る工程と、 その分離された画素間の部分をパッシベーション膜によ
り覆う工程と、 前記第１透明電極層および前記パッシベー ション膜を覆って第２透明電極層を被着する工程と、 該第２透明電極層のうち前記画素間の分離部分に対応す
る部分に光シールド層を配置する工程とを具えたことを
特徴とする固体撮像素子の製造方法。 ３）特許請求の範囲第１項または第２項に記載の固体撮
像素子の製造方法において、前記光導電膜は、光の入射
表面側から深さ方向に、ｐ＾＋形非晶質シリコン膜およ
びｎ形またはｉ形非晶質シリコン膜を配置してなること
を特徴とする固体撮像素子の製造方法。 ４）特許請求の範囲第１項または第２項に記載の固体撮
像素子の製造方法において、前記光導電膜は、光の入射
表面側から深さ方向に、ｐ＾＋形非晶質シリコン膜、ｎ
形またはｉ形非晶質シリコン膜およびｐ＾−形非晶質シ
リコン膜を配置してなることを特徴とする固体撮像素子
の製造方法。[Claims] 1) A photoconductive film and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a scanning circuit for a plurality of pixels, and the plurality of electrodes on the semiconductor substrate and the transparent electrode layer In manufacturing the solid-state imaging device in which the plurality of pixels are partitioned, forming an electrode layer covering the semiconductor substrate to form the plurality of electrodes; and covering the electrode layer. forming the photoconductive film; forming a first transparent electrode layer covering the photoconductive film; and forming a resist pattern corresponding to the plurality of pixels on the first transparent electrode layer. etching the first transparent electrode layer and the photoconductive film using the resist pattern to spatially separate the pixels of the first transparent electrode layer and the photoconductive film; a step of etching the separated first transparent electrode layer and the electrode layer on which the photoconductive film is arranged using the resist pattern, and separating the electrode layer between pixels. A method for manufacturing an image sensor. 2) A photoconductive film and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a scanning circuit for a plurality of pixels, and the plurality of pixels are partitioned by the plurality of electrodes on the semiconductor substrate and the transparent electrode layer. In manufacturing the solid-state imaging device, the steps include: forming an electrode layer covering the semiconductor substrate to form the plurality of electrodes; and forming the photoconductive film covering the electrode layer. forming a first transparent electrode layer covering the photoconductive film; forming a resist pattern corresponding to the plurality of pixels on the first transparent electrode layer; etching the first transparent electrode layer and the photoconductive film using the resist pattern to spatially separate the pixels of the first transparent electrode layer and the photoconductive film; etching the electrode layer on which the transparent electrode layer and the photoconductive film are arranged using the resist pattern, separating the electrode layer between pixels, and covering the separated portion between the pixels with a passivation film. a step of depositing a second transparent electrode layer covering the first transparent electrode layer and the passivation film; and applying a light shield layer to a portion of the second transparent electrode layer corresponding to the separation portion between the pixels. 1. A method for manufacturing a solid-state image sensor, comprising the step of arranging it. 3) In the method for manufacturing a solid-state imaging device according to claim 1 or 2, the photoconductive film is formed of a p^+ type amorphous silicon film in the depth direction from the light incident surface side. and a method for manufacturing a solid-state image sensor, characterized in that an n-type or i-type amorphous silicon film is arranged. 4) In the method for manufacturing a solid-state imaging device according to claim 1 or 2, the photoconductive film is formed of a p^+ type amorphous silicon film in the depth direction from the light incident surface side. ,n
1. A method for manufacturing a solid-state image sensor, comprising arranging a type or i-type amorphous silicon film and a p^-type amorphous silicon film.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59220547A JPS6199370A (en) | 1984-10-22 | 1984-10-22 | Manufacture of solid-state image sensor element |
| US06/790,015 US4694317A (en) | 1984-10-22 | 1985-10-22 | Solid state imaging device and process for fabricating the same |
| US07/077,157 US4735908A (en) | 1984-10-22 | 1987-07-24 | Process for fabricating solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59220547A JPS6199370A (en) | 1984-10-22 | 1984-10-22 | Manufacture of solid-state image sensor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6199370A true JPS6199370A (en) | 1986-05-17 |
| JPH0586867B2 JPH0586867B2 (en) | 1993-12-14 |
Family
ID=16752699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59220547A Granted JPS6199370A (en) | 1984-10-22 | 1984-10-22 | Manufacture of solid-state image sensor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6199370A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2434144A (en) * | 2004-11-10 | 2007-07-18 | Tokiwa Corp | Application content extrusion container |
-
1984
- 1984-10-22 JP JP59220547A patent/JPS6199370A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2434144A (en) * | 2004-11-10 | 2007-07-18 | Tokiwa Corp | Application content extrusion container |
| GB2434144B (en) * | 2004-11-10 | 2008-11-26 | Tokiwa Corp | Fluid extruding container |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0586867B2 (en) | 1993-12-14 |
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