JPS61136263A - Solid-state image pickup device and manufacture thereof - Google Patents
Solid-state image pickup device and manufacture thereofInfo
- Publication number
- JPS61136263A JPS61136263A JP59257687A JP25768784A JPS61136263A JP S61136263 A JPS61136263 A JP S61136263A JP 59257687 A JP59257687 A JP 59257687A JP 25768784 A JP25768784 A JP 25768784A JP S61136263 A JPS61136263 A JP S61136263A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode layer
- solid
- transparent electrode
- pixels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims abstract description 108
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- 238000003384 imaging method Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000000206 photolithography Methods 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 229910052723 transition metal Inorganic materials 0.000 claims description 3
- 150000003624 transition metals Chemical class 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910018594 Si-Cu Inorganic materials 0.000 claims description 2
- 229910008465 Si—Cu Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910018125 Al-Si Inorganic materials 0.000 claims 1
- 229910018520 Al—Si Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 7
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 230000003287 optical effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 230000003628 erosive effect Effects 0.000 abstract 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229920000742 Cotton Polymers 0.000 description 1
- 229910019974 CrSi Inorganic materials 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 101100219440 Schizosaccharomyces pombe (strain 972 / ATCC 24843) cao2 gene Proteins 0.000 description 1
- 206010047571 Visual impairment Diseases 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 235000012054 meals Nutrition 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000007591 painting process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 210000001747 pupil Anatomy 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/09—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/095—Devices sensitive to infrared, visible or ultraviolet radiation comprising amorphous semiconductors
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
開明の稜術分野
本発明は、半導体基板上に定食回路および光導電膜ｉＦ
ｃＦｃ化した固体撮像素子、特に複数の画業の足前回路
を設けた半導体基板上に光導電膜および透明電極層をこ
の順序で配置し、前記半導体基板ｔの複数の電極と前記
透明電極層とにより前記複数の画ａｔ−区画するように
した固体撮像素子およびその製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention provides a method for fabricating a fixed circuit and a photoconductive film iF on a semiconductor substrate.
A photoconductive film and a transparent electrode layer are arranged in this order on a cFc solid-state image sensor, in particular, a semiconductor substrate provided with a plurality of front circuits for imaging, and the plurality of electrodes of the semiconductor substrate t and the transparent electrode layer are The present invention relates to a solid-state imaging device in which the plurality of images are divided into sections, and a method for manufacturing the same.
従米稜術とその問題照
この種積層型の固体撮像素子においては、光感度を品め
るために、光導電ｇ ｉ ＭＯＳ型、 ＣＣＤ型あるい
は８ＢＤ型の走査回路基板上に積層させている。ここで
、積層される光導電層を１！１続して平面法に配置する
ことが考えられるが、その場合に、光導電層として非晶
質シリコンを利用した固体撮像素子に８いては、平面方
間の抵抗か他の材料に比べて若干低いため、解像度が大
さく劣化し、混色も大さい、この欠点を除去Ｔべく非晶
質シリコン膜を面抵抗化した場合、キャリア移動食か低
下したり、トラップ密潰の増加に住なうＰｉ像の増力ｌ
Ｉなどの欠、鑞かめった。In this type of stacked solid-state image sensing device, in order to improve the photosensitivity, it is stacked on a photoconductive MOS type, CCD type, or 8BD type scanning circuit board. Here, it is conceivable to arrange the photoconductive layers to be laminated one after another in a planar method, but in that case, in a solid-state image sensor using amorphous silicon as the photoconductive layer, Since the resistance in the plane direction is slightly lower than that of other materials, the resolution deteriorates greatly and the color mixture is also large.If the amorphous silicon film is made into a sheet resistor to eliminate this drawback, carrier migration attack will occur. Increased power of Pi statue that decreases or increases trap crushing
The lack of letters such as I was a big hit.
そこで、光導電ｔｔＪｔ−画素毎に分離して配＃するこ
とか考えられるか、その場合に、分厚し、めるいは層間
絶縁層に開口をめげるためのエツチング処理時に光４電
層か不所望に侵食されて短絡してしまうおそれかめる。Therefore, is it possible to consider separately distributing the photoconductor ttJt for each pixel? In that case, it would be possible to thicken the photoconductive layer or remove undesired photoconductor layers during the etching process to create an opening in the interlayer insulating layer. There is a risk that it will be eroded by the heat and cause a short circuit.
ざらにまた、分厚した光導電層の厚ざか０．５〜５鉢−
と厚いので、これによる段差部分において、透明電極層
は段差切れを生じや丁い。In addition, the thickness of the thick photoconductive layer is 0.5 to 5.
Since the transparent electrode layer is thick, the transparent electrode layer may be cut off at the step portion due to this.
発明の目的
そこで、本発明の目的は、上述した解像度の劣化や混色
の発生という欠点を除去するために、非晶質シリコン膜
を画業毎に分離させると共に、その際に光導電層の分離
処理を適切に行うことかでさ、かつ段差ν）れなどの欠
陥が発生しないようにＩＩ！ｙノに構成した固体撮像素
子を提供することにゐる。OBJECT OF THE INVENTION Therefore, an object of the present invention is to separate the amorphous silicon film for each image, in order to eliminate the above-mentioned drawbacks such as deterioration of resolution and occurrence of color mixture, and at the same time, to separate the photoconductive layer. To prevent defects such as cracks and cracks from occurring, II! The purpose of the present invention is to provide a solid-state imaging device having a unique structure.
木光明の池の目的は、ｆ：述した解像度の劣化や混色の
発生という火照を除去Ｔるために、非晶質シリコン膜を
画業毎に分離させると共に、その際に光４蒐層の分離処
理を適切に施し、かつ段差切れなどの欠陥が発生しない
ように５ｔＪＪに処理工程を進め、しかも工程の簡略化
を図った固体撮像素子の装造方法を提供することにみる
。The purpose of Kikomei no Ike is to separate the amorphous silicon film for each painting process, and at the same time to separate the four layers of light in order to eliminate the problems of resolution deterioration and color mixing mentioned above. It is an object of the present invention to provide a method for assembling a solid-state image sensor in which processing is performed appropriately, the processing steps are advanced to 5tJJ to prevent defects such as step breaks, and the steps are simplified.
発明の構成
かかる目的を達成するために、本発明固体ｉｊ１像素子
では、複数の画業の走査回路ｔ−設けた半導体基板上に
感光層および透明電極層をこの１−序で配置し、半導体
基板上の複数の電極と透明″ＲＬ権層極層より複数の画
業を区画するようにした固体撮像素子において、感光層
か画業毎に分離され、画素間の分ｇ１溝８よび画素毎に
分離された感光層の周縁を覆って層間絶縁膜を配置し、
その層間絶１＆膜ｆ：情って透明電極＃を配置し、その
透明″？［極層ｔの画素間領域に光シールド用金属Ｗ！
を配置したことを特徴とする。Structure of the Invention In order to achieve the above object, in the solid-state image element of the present invention, a photosensitive layer and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a plurality of imaging scanning circuits. In a solid-state imaging device in which a plurality of image areas are partitioned from a plurality of electrodes and a transparent "RL right layer" on the polar layer, the photosensitive layer is separated for each image area, and is separated for each pixel by the groove 8 between pixels. An interlayer insulating film is placed to cover the periphery of the photosensitive layer.
The layer interlayer 1 & film f: A transparent electrode # is arranged, and the transparent electrode # is placed in the interpixel region of the layer t.
It is characterized by having been placed.
本発明製造方法は、複数の画素の定食回路を設けた半導
体基板上に光導電膜および透明電極層をこの順序で配置
し、半導体基板上の複数の電極と透明電８１層とにより
複数の画素を区画Ｔるようにした１ｉｉｉｉ体（＃Ｉ像
素子を製造するにあたり、祷叡の電極を構成するための
電極層を半導体基板上を覆って形成する工程と、電極層
の上を覆って光導電膜そ形成する工程と、電極層８Ｊ：
び光導電膜を、復叡の画素に対応してガｇＦさせるフー
オトリングラフィ１稈と、それにより分離された光導電
１θおよび画素間の分屋された領域を覆って層間絶縁膜
を付宥させる工程と２層間絶縁膜のうち複数の画素に対
応して開口を形成Ｔるフォトリングラフィ工程と、開口
のめいた層間？ｅ縁膜およびその開口により７１ｍ丁６
党導ＩＩＥ膜を覆って透明電極層を形成する工程と、こ
の透明電極層のうち画素間領域に対応する部分の上に光
シールド用の４？？属＃を形成Ｔる工程とｔ−具えたこ
とを特徴とする。In the manufacturing method of the present invention, a photoconductive film and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a set circuit for a plurality of pixels, and a plurality of pixels are formed by the plurality of electrodes and the transparent electrode layer on the semiconductor substrate. In manufacturing the 1III image element (#I) in which the image element is divided into sections T, there are two steps: forming an electrode layer covering the semiconductor substrate to form the electrode of the prayer, and a step of forming an electrode layer covering the semiconductor substrate to form the electrode layer. Step of forming the conductive film and electrode layer 8J:
A photoconductive layer is applied to the photoconductive film to cover the separated photoconductive layer 1θ and the divided area between the pixels, and an interlayer insulating film is applied thereto. A softening process, a photolithography process in which openings are formed corresponding to a plurality of pixels in the two-layer insulating film, and an interlayer where the openings are formed. e 71 m by the membrane and its opening 6
A step of forming a transparent electrode layer covering the conductive IIE film, and a step of forming a transparent electrode layer for light shielding on the portion of the transparent electrode layer corresponding to the inter-pixel region. ? The method is characterized by comprising a step of forming a genus # and a t-.
発明の実Ｍ例 以ドに、−面そ参照して、不発明の詳細な説明する。Actual example of invention The invention will now be described in detail with reference to the following.
嶋１図（Ａ）〜（Ｄ）は本発明固体装置素子の製造方法
の順次の工程の一例を示し、ここで、１００は定食回路
基板、２００は光導電膜部分を示す０走査回路基板１０
０は公知のいかなる形態であってもよく、例えば１Ｍ０
９型素子、 ＣＣＯあるいは８８０で構成でさる。以ド
では、その−例として、ＭＯＳ型素子により定食回路基
板１００を構成してボす。Shima 1 Figures (A) to (D) show an example of the sequential steps of the method for manufacturing a solid-state device element of the present invention, where 100 is a set circuit board, and 200 is a 0-scan circuit board 10 indicating a photoconductive film portion.
0 may be in any known form, for example 1M0
It consists of a 9-type element, CCO or 880. Hereinafter, as an example, a set meal circuit board 100 will be constructed using MOS type elements.
１公わち、定食回路基板１００は、ソースｌ、トレイン
２８よひゲート３から成るＭＯ９″ｉｌｊ：界効果トラ
ンジスタｔ−有し、各ＭＯ８電界効果トランジスタ藺を
５ｉ０２絶縁層４で分離する。ケート３はＰＳＧ（リン
シリケートカラス）あるいは５１０２による絶縁＃５に
埋め込まれている。６はソースｌに接続された電極であ
り、この電極６をρＳＧ、 Ｓ＋１）２Ｓ＋ｍＮ４Ｐす
るいはポリイミド等の有機物による＃ｅ縁層７により覆
って、その上に、ソース１に接続され、倹述する工程を
経てからｌｌ！！！素を区画するＴｌＬａ＋層８を一様
に配置する。電極層８としてはＡＭ −３ｉ 、 Ａ
ｎ −Ｓｉ−ＣｕＸたはＭＯなどのａ移労属ご用いるこ
とかでさる。1. Specifically, the fixed circuit board 100 has an MO8 field effect transistor t- consisting of a source 1, a train 28 and a gate 3, and each MO8 field effect transistor is separated by a 5i02 insulating layer 4. 3 is embedded in insulation #5 made of PSG (phosphosilicate glass) or 5102. 6 is an electrode connected to the source 1, and this electrode 6 is made of #5 made of an organic material such as ρSG, S+1)2S+mN4P or polyimide. Covered with the e-edge layer 7, a TlLa+ layer 8 connected to the source 1 and partitioning the ll!!! element after going through the steps described above is uniformly arranged on it. 3i, A
It depends on whether you use a transfer metal such as n-Si-CuX or MO.
本発明では、８１図（Ａ）に示すように、光導電膜部分
２００を、平担なド地１Ｍ、権８の上に形成Ｔる。Ｔな
わち、ドＸ！！電極８の上に１丁ノンドープのままのｎ
ｆ’ ＃品質シリコン膜またはボロンを添那した高抵
抗のｉ形の丼晶賀シリコンｍ９１Ｉｅ配置し、このｎ形
（、１＃） Ｊ＋”品質シリコン膜９のヒに不純物添厘
によるｐ十形非品質シリコン膜ｌＯを配置する。In the present invention, as shown in FIG. 81(A), a photoconductive film portion 200 is formed on a flat dot 1M and a dot 8. T, in other words, Do-X! ! One undoped n on the electrode 8
f'# quality silicon film or boron doped high resistance i type silicon m91Ie is arranged, this n type (, 1 #) A non-quality silicon film IO is placed.
つぎに、第１図（＾）に、９線で示Ｔように、ｐ＋形井
墨買シリコン膜ｌＯ上に１素ｍ域に対応してレジストパ
ターン１２を１１看してからエンチングを行い、第１図
ＣＢ＞に示すように１画素間の分離＃１１１３を形成し
、それによって光導電膜部分２００に対してｌ！ｌＩＮ
素間の分Ｈを行う。Next, as shown by line 9 in FIG. 1(^), a resist pattern 12 corresponding to one element m area is etched on the p+ type silicon film lO after being etched for 11 times. A separation #1113 between one pixel is formed as shown in FIG. IN
Perform H for the bare time.
ざらに、第１図（Ｂ）にボＴように、溝１３に、膚労敲
の層間？ｅ縁膜１４としてプラズマＳ＋３Ｎａ 。Roughly, as shown in Fig. 1 (B), there is an interlayer of the skin in the groove 13? e Plasma S+3Na as the membrane 14.
Ｓ＋０． 、ＰＳＧなどの無機物やポリイミドなどの有
ａ物をプラズマＣｖＯ法などによって付置させる。S+0. , an inorganic material such as PSG or an amorphous material such as polyimide is deposited by a plasma CvO method or the like.
次に、この層間ＮＡ縁層１４を、第１図（Ｃ）にボアよ
うに、画業領域に対応して選択的にエンチング処理して
、コンタクト開口１５ｔ−形成する。Next, this interlayer NA edge layer 14 is selectively etched to form a contact opening 15t corresponding to the image area, such as a bore as shown in FIG. 1(C).
ここで、ｐ＋形丼晶貢シリコンｆｉｌＯのシート抵抗を
小ざく、例えばその比抵抗ρ≦１０’Ωｃｍ、好ましく
はρ≦１０’ΩＣ１１に定めて、ドライエツチング処８
Ｉを適切に行うことにより ｐ＋形葬品質シリコン膜ｌ
Ｏが侵食されないようにする。なお、走査回路基板１０
Ｇ上に８０９回路を組込むと５にはρ≦１０’ΩＣ■と
し、ＣＣＯ回路回路組込むと５にはρ≦１０’ΩＣ層と
丁ればよい。Here, the sheet resistance of the p+ type crystalline silicon filO is set to be small, for example, its specific resistance ρ≦10′Ωcm, preferably ρ≦10′ΩC11, and the dry etching process 8
By properly performing I, p+ molding quality silicon film l
Prevent O from being eroded. Note that the scanning circuit board 10
When an 809 circuit is incorporated on G, ρ≦10′ΩC for 5, and when a CCO circuit is incorporated, ρ≦10′ΩC for 5.
ざらに、第１図（０）にボＴように、透明電極層１１お
よびこのような開口１５の形成された層間ｌｐ！ｆｉＲ
膜１４を覆って全面に透明電極層１Ｂを厚ざ５００〜３
０００ Ａ程度に１１看する。この透明電極層１６はＩ
ＴＯ、ＳｎＯ３ 、 ［ｎｓＬ＋）３ 、ＣｄＯ２）
Ｃｒ−５ｉｚどの’ｕ料で形成でさる。その透明電極層
１８のうち、画素量分！領域には金属による光シールド
層１７を板前する。光シールド層１７ｉ形成する金属と
しては。Roughly, as shown in FIG. 1(0), the transparent electrode layer 11 and the interlayer lp! where such an opening 15 is formed. fiR
A transparent electrode layer 1B is formed on the entire surface covering the membrane 14 with a thickness of 500 to 3
000 A for 11 minutes. This transparent electrode layer 16 is
TO, SnO3, [nsL+)3, CdO2)
Cr-5iz can be formed from any material. Of the transparent electrode layer 18, the amount corresponds to the pixel amount! A light shield layer 17 made of metal is placed in front of the area. The metal used to form the optical shield layer 17i is as follows.
１１Ｊｊ、Ａ父−Ｓｉ 、Ａｎ −Ｓｉ−Ｃｕ ７た
はＮｏ、Ｗ、Ｃｒ、Ｔａなとの遷移金属を用いることか
でさる。 □なお、１例では、光４電膜部分は、表
面側からｐ！−形丼晶賀シリコンｄｌＱ−ｎ形（ｉ形）
丼墨質シリコン膜９か配置された構造としたか、ド地電
極８とｎ形（ｉ形）丼晶簀シリコン膜９との間にｐ−形
井品質シリコン膜を配置した構造としてもよｌ／）。11Jj, A-Si, An-Si-Cu 7 or using transition metals such as No, W, Cr, and Ta. □In one example, the photovoltaic film portion is p! from the surface side. - Shape bowl Ayoga silicon dlQ-n type (i type)
It is also possible to adopt a structure in which a bowl crystalline silicon film 9 is disposed, or a structure in which a p-type well quality silicon film is disposed between the ground electrode 8 and the n-type (i-type) bowl crystal silicon film 9. l/).
発明の効果
以上から明らかなように１本発明によれば、ｐｎｉ 書
間が完全に分ｐＩｉされているので、解像俄の劣化およ
び混色の発生を完全に防１ヒできる。感光層を形成する
ｐ◆形非晶簀シリコン瞳の比抵抗を１０′ΩＣ厘以下な
どのように低い値に定めることにより、層間絶縁膜に開
口を形成するためのプラズマエツチングなどのドライエ
ッチ／りを行うにゐたって、かかるｐ÷形フ「晶貢シリ
コン膜は、特にその虹にエツチングに対する保護層を設
けなくとも侵１をされずにすみ、保護層を股６する横這
および工８！を経る必要がない利点もめる。Effects of the Invention As is clear from the foregoing, according to the present invention, since the pni inter-paper interval is completely divided into pIi, it is possible to completely prevent deterioration during resolution and occurrence of color mixture. By setting the specific resistance of the p◆ type amorphous silicon pupil forming the photosensitive layer to a low value such as 10'ΩC or less, dry etching such as plasma etching to form an opening in the interlayer insulating film can be performed. When carrying out the etching process, such a p÷ type silicon film does not suffer from attack even if a protective layer against etching is not provided on the surface of the film. The advantage of not having to go through !
ざらにＭえて、本発明により形成された一俸撮塚、素子
は、十面万同の抵抗か低くても移動度か大さく、かつト
ラップ密廉の小ざい膜組成を利用でさるので、坦数長分
光感度が劣化せず、かつ、残像の少ない特性を得ること
かでさる。ざらにまた、光シールド層上金属層で形成↑
るので１分難倹に透明電ａ層を形成するにあたり、たと
えこの透明１１極層か分離溝の奥深く入りこまなくとも
、このｅ属層か導電性を保証することがでさ、したがっ
て、ａ明電極層の段差切れなどが生じても、そのｇ影響
を受けない。Roughly speaking, the device formed according to the present invention has a low resistance on all sides, a high mobility, and a small film composition with a small trap density. The key is to obtain characteristics that do not deteriorate the spectral sensitivity of the carrier number length and have fewer afterimages. In addition, a metal layer is formed on the light shield layer↑
Therefore, when forming the transparent conductive a layer in less than 1 minute, even if this transparent 11-pole layer does not go deep into the separation groove, the conductivity of this e-group layer can be guaranteed. Even if a break in the bright electrode layer occurs, it will not be affected by the g.
第１図（Ａ）〜（Ｄ）は本発明における一曲の製造上程
を示す断面図である。
１００・・・走査回路基板、■・・・ソース、２・・・
ドレイン、３・・・ケート、４・・・絶縁層、５・・・
絶縁層、６・・・’を権、７・・・絶縁層、８・・・ド
坩電極、２００・・・光導を膜部分、９・・・ｎ （：
ｉ）形葬晶質シリコン膜、ＩＱ・・・ｐ＋形丼晶懺シリ
コン膜、１２・・・レシストバクーン、 １３・・・分
離溝、１４・・・層間絶縁膜、 １５・・・コンタクト
開口、＋１３・・・透明″ｆｌＬ極層、１７・・・光シ
ールド層。
手続７市正書 １．明細書特許庁長官 志
賀 学 殿 ２° ＃４′８Ｉ書ｒ
５ｎ０３
１、事件の表示 ｒ
５ｎ０７特願昭５９−２５７６８７号
２）発明の名称
固体撮像素子およびその１遣方法
３、補正をする者
事件との関係 特許出願人
富士写真フィルム株式会社
４、代理人
住 所 〒１０５
東京都港区虎ノ門２丁目３番２２号
秋山ビＪ１７９Ｆ 電話（０３）５０８−８３８８
−氏 名 （９０Ｂ？）弁理°士 永 島
孝 明 １ ′ °）５、補正命令の日付 自
発
６、補正の対象
明細書の「２）特許請求の範囲」の欄
の「２）特許請求の範囲」を別紙の通りの第１Ｏ頁第１
３行目の
、 Ｉｎ４Ｑ３ 、ＣｄＯ２）Ｃｒ−５ｉＪを、 Ｉｎ
２Ｏ２，ＣｄＯ２）ＣｒＳｉ、、 ４に訂正する。
以ヱ
特許請求の範囲
ｌ） 複数の画素の走査回路を設けた半導体基板上に感
光層および透明電極層をこの順序で配置し、前記半導体
基板上の複数の電極と前記透明電極層とにより前記複数
の画素を区画するようにした固体撮像素子において。
前記感光層が画素毎に分離され、前記画素Ｊｕｌ＋の分
＃溝および前記画素毎に分離された感光層の周縁を甲っ
て居間綿ｔｉｋｌＩを配置し、該層間絶縁膜を覆って透
明電極層を配置し、該透明電極層ヒの画素間領域に光シ
ールド用金属層を配置したことを特徴とする固体撮像妻
子。
２）特許請求の範囲第１項記載の固体撮像素子において
、前記感光層は水票化非晶質シリコン層であることを特
徴とする固体撮像素子。
３）特許請求の範囲第１項または第２項記載の固体撮像
素子において、前記透明電極層はＩＴＯ、ＳｎＯ２
、 ＩｎＬ０３ 、ｃａｏ２． Ｃｒ５ｉ）（テあるこ
とを特徴とする固体撮像素子。
４）特許請求の範囲＠１項ないし第３項のいずれかの項
に記載の固体撮像妻子において、前記光シールド用金属
層はＡｆＬ、ＡＪｌ −Ｓｉ、 Ａｉ −Ｓｉ−Ｃｕ。
またはＭｏ、Ｗ、Ｃｒ、Ｔａなどの遷移金属であること
を特徴とする固体撮像素子。
５）特許請求の範囲第２項ないし第４項のいずれかの項
に記載の固体撮像妻子において、前記感光層のうち、前
記透明電極層と接する側の層の比抵抗を１０７０ｃｍ以
下としたことを特徴とする固体撮像素子。
６）複数の画素の走査回路を設けた半導体基板トに光導
電膜および透明電極層をこの順序で配置し、前記半導体
基板上の複数の電極と前記透明電極層とにより前記複数
の画素を区画するようにした固体撮像素子を製造するに
あたり、前記複数の電極を構成するための電極層を前記
半導体基板上を覆って形成する工程と、前記電Ｊｉ層の
上を覆って前記光導電膜を形成する工程と、
前記電極層および前記光導″＄、ＩＩｇを、而記複数の
画素に対応して分離させるフォトリソグラフィ工程と。
分離された前記光導電膜および画素間の分離された領域
を覆って居間絶縁膜を付着させる工程と。
該層間絶縁膜のうち前記複数の画素に対応して開口を形
成するフォトリングラフィ工程と、
前記開口のあいた層間絶縁膜および当該開口により露出
する前記光導電膜を層って透明電極層を形成する工程と
。
該透明電極層のうち前記画素間領域に対応する部分の上
に光シールド用の金属層を形成する工程とをルえたこと
を特徴とする固体撮像素子の智造方法。FIGS. 1A to 1D are cross-sectional views showing the manufacturing process of one piece of music according to the present invention. 100...Scanning circuit board, ■...Source, 2...
Drain, 3... Kate, 4... Insulating layer, 5...
Insulating layer, 6...', 7... Insulating layer, 8... Crucible electrode, 200... Membrane portion for light guide, 9...n (:
i) Shaped crystalline silicon film, IQ...p+ type crystalline silicon film, 12... Resist bubble, 13... Isolation groove, 14... Interlayer insulating film, 15... Contact opening , +13...Transparent"flL polar layer, 17...Light shield layer. Procedure 7 official document 1. Specification Patent Office Commissioner Manabu Shiga 2° #4'8I letter r
5n03 1. Display of incident r
5n07 Japanese Patent Application No. 59-257687 2) Title of the invention: Solid-state imaging device and its method 3; Relationship with the person making the amendment Patent applicant: Fuji Photo Film Co., Ltd. 4; Agent address: 105 Port of Tokyo Akiyama Bi J179F, 2-3-22 Toranomon, Tokyo Tel: (03) 508-8388
-Name (90B?) Patent attorney Nagashima
Takaaki 1' °) 5. Date of amendment order From
Issue 6, "2) Scope of claims" in the column "2) Scope of claims" of the specification to be amended shall be changed to page 10, No. 1, as shown in the attached document.
In the third line, In4Q3,CdO2)Cr-5iJ, In
2O2,CdO2)CrSi,, Corrected to 4. Claims l) A photosensitive layer and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a scanning circuit for a plurality of pixels, and the plurality of electrodes on the semiconductor substrate and the transparent electrode layer In a solid-state image sensor that partitions a plurality of pixels. The photosensitive layer is separated for each pixel, and living room cotton tiklI is placed over the groove of the pixel Jul+ and the periphery of the photosensitive layer separated for each pixel, and a transparent electrode layer is placed to cover the interlayer insulating film. A solid-state imaging device, characterized in that a metal layer for light shielding is arranged in the inter-pixel region of the transparent electrode layer H. 2) A solid-state image sensor according to claim 1, wherein the photosensitive layer is a water-linked amorphous silicon layer. 3) In the solid-state imaging device according to claim 1 or 2, the transparent electrode layer is made of ITO, SnO2
, InL03, cao2. Cr5i) (A solid-state imaging device characterized by having Te. 4) In the solid-state imaging wife and child according to any one of claims @1 to 3, the light shielding metal layer is AfL, AJl. -Si, Ai -Si-Cu. Or a solid-state imaging device characterized by being made of a transition metal such as Mo, W, Cr, or Ta. 5) In the solid-state imaging wife and child according to any one of claims 2 to 4, the specific resistance of the layer in contact with the transparent electrode layer of the photosensitive layer is 1070 cm or less. A solid-state image sensor featuring: 6) A photoconductive film and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a scanning circuit for a plurality of pixels, and the plurality of pixels are partitioned by the plurality of electrodes on the semiconductor substrate and the transparent electrode layer. In manufacturing the solid-state image sensing device, the method includes a step of forming an electrode layer covering the semiconductor substrate to form the plurality of electrodes, and a step of forming the photoconductive film by covering the top of the electrical conductive layer. and a photolithography step of separating the electrode layer and the light guide layer IIg corresponding to a plurality of pixels. a step of attaching a living room insulating film through the interlayer insulating film; a photolithography step of forming openings in the interlayer insulating film corresponding to the plurality of pixels; A step of forming a transparent electrode layer by layering a film; and a step of forming a metal layer for light shielding on a portion of the transparent electrode layer corresponding to the inter-pixel region. Chi-manufacturing method for solid-state image sensors.
Claims (1)
層および透明電極層をこの順序で配置し、前記半導体基
板上の複数の電極とを前記透明電極層とにより前記複数
の画素を区画するようにした一体撮像素子において、 前記感光層が画素毎に分離され、前記画素間の分離溝お
よび前記画素毎に分離された感光層の周縁を覆って層間
絶縁膜を配置し、該層間絶縁膜を覆って透明電極層を配
置し、該透明電極層上の画素間領域に光シールド用金属
層を配置したことを特徴とする固体撮像素子。 ２）特許請求の範囲第１項記載の固体撮像素子において
、前記感光層は水素化非晶質シリコン層であることを特
徴とする固体撮像素子。 ３）特許請求の範囲第１項または第２項記載の固体撮像
素子において、前記透明電極層は ＩＴＯ、ＳｎＯ＿３、Ｉｎ＿２Ｏ＿３、ＣｄＯ＿２、Ｃ
ｒ−Ｓｉであることを特徴とする固体撮像素子。 ４）特許請求の範囲第１項ないし第３項のいずれかの項
に記載の固体撮像素子において、前記光シールド用金属
層はＡｌ、Ａｌ−Ｓｉ、Ａｌ−Ｓｉ−Ｃｕ、またはＭｏ
、Ｗ、Ｃｒ、Ｔａなどの遷移金属であることを特徴とす
る固体撮像素子。 ５）特許請求の範囲第２項ないし第４項のいずれかの項
に記載の固体撮像素子において、前記感光層のうち、前
記透明電極層と接する側の層の比抵抗を１０＾７Ωｃｍ
以下としたことを特徴とする固体撮像素子。 ６）複数の画素の走査回路を設けた半導体基板上に光導
電膜および透明電極層をこの順序で配置し、前記半導体
基板上の複数の電極と前記透明電極層とにより前記複数
の画素を区画するようにした固体撮像素子を製造するに
あたり、 前記複数の電極を構成するための電極層を前記半導体基
板上を覆って形成する工程と、 前記電極層の上を覆って前記光導電膜を形成する工程と
、 前記電極層および前記光導電膜を、前記複数の画素に対
応して分離させるフォトリソグラフィ工程と、 分離された前記光導電膜および画素間の分離された領域
を覆って層間絶縁膜を付着させる工程と、 該層間絶縁膜のうち前記複数の画素に対応して開口を形
成するフォトリソグラフィ工程 と、 前記開口のあいた層間絶縁膜および当該開口により露出
する前記光導電膜を覆って透明電極層を形成する工程と
、 該透明電極層のうち前記画素間領域に対応する部分の上
に光シールド用の金属層を形成する工程とを具えたこと
を特徴とする固体撮像素子の製造方法。[Claims] 1) A photosensitive layer and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a scanning circuit for a plurality of pixels, and a plurality of electrodes on the semiconductor substrate are connected to the transparent electrode layer. In the integrated image sensor in which the plurality of pixels are partitioned, the photosensitive layer is separated for each pixel, and an interlayer insulating film is provided covering the separation groove between the pixels and the periphery of the photosensitive layer separated for each pixel. A solid-state image sensor, comprising: a transparent electrode layer disposed to cover the interlayer insulating film; and a light shielding metal layer disposed in an inter-pixel region on the transparent electrode layer. 2) A solid-state image sensor according to claim 1, wherein the photosensitive layer is a hydrogenated amorphous silicon layer. 3) In the solid-state imaging device according to claim 1 or 2, the transparent electrode layer is made of ITO, SnO_3, In_2O_3, CdO_2, C
A solid-state imaging device characterized by being r-Si. 4) In the solid-state imaging device according to any one of claims 1 to 3, the light shielding metal layer is made of Al, Al-Si, Al-Si-Cu, or Mo.
, W, Cr, Ta, or other transition metals. 5) In the solid-state imaging device according to any one of claims 2 to 4, the resistivity of the layer in contact with the transparent electrode layer of the photosensitive layer is 10^7 Ωcm.
A solid-state imaging device characterized by the following. 6) A photoconductive film and a transparent electrode layer are arranged in this order on a semiconductor substrate provided with a scanning circuit for a plurality of pixels, and the plurality of pixels are partitioned by the plurality of electrodes on the semiconductor substrate and the transparent electrode layer. In manufacturing the solid-state imaging device, the steps include: forming an electrode layer covering the semiconductor substrate to form the plurality of electrodes; and forming the photoconductive film covering the electrode layer. a photolithography step of separating the electrode layer and the photoconductive film corresponding to the plurality of pixels; and forming an interlayer insulating film covering the separated photoconductive film and the separated region between the pixels. a photolithography step of forming openings corresponding to the plurality of pixels in the interlayer insulating film, and a transparent film covering the interlayer insulating film with the opening and the photoconductive film exposed by the opening. A method for manufacturing a solid-state imaging device, comprising: forming an electrode layer; and forming a metal layer for light shielding on a portion of the transparent electrode layer corresponding to the inter-pixel region. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59257687A JPS61136263A (en) | 1984-12-07 | 1984-12-07 | Solid-state image pickup device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59257687A JPS61136263A (en) | 1984-12-07 | 1984-12-07 | Solid-state image pickup device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61136263A true JPS61136263A (en) | 1986-06-24 |
Family
ID=17309711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59257687A Pending JPS61136263A (en) | 1984-12-07 | 1984-12-07 | Solid-state image pickup device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61136263A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5899547A (en) * | 1990-11-26 | 1999-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US6013928A (en) * | 1991-08-23 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having interlayer insulating film and method for forming the same |
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
-
1984
- 1984-12-07 JP JP59257687A patent/JPS61136263A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5899547A (en) * | 1990-11-26 | 1999-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US5946059A (en) * | 1990-11-26 | 1999-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US7423290B2 (en) | 1990-11-26 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US6013928A (en) * | 1991-08-23 | 2000-01-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having interlayer insulating film and method for forming the same |
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