JPS6197857U - - Google Patents
Info
- Publication number
- JPS6197857U JPS6197857U JP18404484U JP18404484U JPS6197857U JP S6197857 U JPS6197857 U JP S6197857U JP 18404484 U JP18404484 U JP 18404484U JP 18404484 U JP18404484 U JP 18404484U JP S6197857 U JPS6197857 U JP S6197857U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring board
- circuit wiring
- semiconductor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例による半導体装置の
平面図、第２図は第１図の−線断面図、第３
図は従来の半導体装置の平面図、第４図は第３図
の−線断面図である。
１は絶縁基板（回路配線基板）、２は導体層、
４は半導体素子である。なお図中同一符号は同一
又は相当部分を示す。
FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the - line in FIG.
The figure is a plan view of a conventional semiconductor device, and FIG. 4 is a sectional view taken along the line -- in FIG. 1 is an insulating substrate (circuit wiring board), 2 is a conductor layer,
4 is a semiconductor element. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
素子が実装されてなる半導体装置において、２個
の半導体素子がその回路形成面が、上記回路配線
基板側に向くように、該基板の両面に実装されて
いることを特徴とする半導体装置。 (2) 上記回路配線基板がテープフイルム状とな
つていることを特徴とする実用新案登録請求の範
囲第１項記載の半導体装置。[Claims for Utility Model Registration] (1) In a semiconductor device in which semiconductor elements are mounted on a circuit wiring board on which a conductor layer is formed, two semiconductor elements have their circuit forming surfaces facing the circuit wiring board side. A semiconductor device, characterized in that the semiconductor device is mounted on both sides of the substrate so as to face each other. (2) The semiconductor device according to claim 1, wherein the circuit wiring board is in the form of a tape film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18404484U JPS6197857U (en) | 1984-12-03 | 1984-12-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18404484U JPS6197857U (en) | 1984-12-03 | 1984-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6197857U true JPS6197857U (en) | 1986-06-23 |
Family
ID=30741530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18404484U Pending JPS6197857U (en) | 1984-12-03 | 1984-12-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6197857U (en) |
-
1984
- 1984-12-03 JP JP18404484U patent/JPS6197857U/ja active Pending
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