JPS6195124U - - Google Patents

Info

Publication number
JPS6195124U
JPS6195124U JP17927484U JP17927484U JPS6195124U JP S6195124 U JPS6195124 U JP S6195124U JP 17927484 U JP17927484 U JP 17927484U JP 17927484 U JP17927484 U JP 17927484U JP S6195124 U JPS6195124 U JP S6195124U
Authority
JP
Japan
Prior art keywords
counter
memory
receiver
automatic
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17927484U
Other languages
Japanese (ja)
Other versions
JPH0445294Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984179274U priority Critical patent/JPH0445294Y2/ja
Publication of JPS6195124U publication Critical patent/JPS6195124U/ja
Application granted granted Critical
Publication of JPH0445294Y2 publication Critical patent/JPH0445294Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Circuits Of Receivers In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例よりなる受信機のブ
ロツク図、第2図は第1図のa〜d部の信号のス
タート・リセツトを示すタイミングチヤート、第
3図は第1図のa〜l部の信号のカウント・アツ
プを示すタイミングチヤート、および第4図は従
来の受信機のブロツク図である。 8…PLL、9…レベル検出回路、10…発振
器、12…バイナリカウンタ、13…カウンタ、
14…メモリ、18…カウンタ、19…ドライバ
、20…表示器。
FIG. 1 is a block diagram of a receiver according to an embodiment of the present invention, FIG. 2 is a timing chart showing the start and reset of signals in parts a to d of FIG. 1, and FIG. 3 is a FIG. 4 is a timing chart showing the count up of the signals in the .about.l section, and a block diagram of a conventional receiver. 8... PLL, 9... Level detection circuit, 10... Oscillator, 12... Binary counter, 13... Counter,
14...Memory, 18...Counter, 19...Driver, 20...Display device.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 局部発振周波数をフエーズロツクループ(PLL)
で制御し、該PLLの分周比のデータを記憶する
メモリと該メモリをアドレスするカウンタとを有
し、自動プリセツト機能を持つ受信機において、
前記カウンタがオーバーフローしたときに作動す
るカウンタを別途設けるとともに、該カウンタの
データを受けて作動する表示器を設けることによ
り、受信バンドを一巡して自動プリセツト用に用
意されている前記メモリのエリアの数以上の放送
局が受信されたとき、該メモリにプリセツトされ
なかつた放送局の数を前記表示器に表示するよう
にしたことを特徴とする受信機。
The local oscillation frequency is changed to a phase lock loop (PLL).
In a receiver having an automatic preset function, the receiver has a memory for storing frequency division ratio data of the PLL and a counter for addressing the memory, and has an automatic preset function.
By separately providing a counter that operates when the counter overflows, and by providing a display that operates in response to data from the counter, the area of the memory prepared for automatic presetting can be read by going around the reception band. 1. A receiver according to claim 1, wherein when more than one broadcast station is received, the number of broadcast stations that have not been preset in the memory is displayed on the display.
JP1984179274U 1984-11-28 1984-11-28 Expired JPH0445294Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984179274U JPH0445294Y2 (en) 1984-11-28 1984-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984179274U JPH0445294Y2 (en) 1984-11-28 1984-11-28

Publications (2)

Publication Number Publication Date
JPS6195124U true JPS6195124U (en) 1986-06-19
JPH0445294Y2 JPH0445294Y2 (en) 1992-10-26

Family

ID=30736832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984179274U Expired JPH0445294Y2 (en) 1984-11-28 1984-11-28

Country Status (1)

Country Link
JP (1) JPH0445294Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816729U (en) * 1981-07-24 1983-02-02 シャープ株式会社 automatic paper feeder
JPS58169723U (en) * 1982-05-01 1983-11-12 アルパイン株式会社 radio receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816729B2 (en) * 1978-12-12 1983-04-01 富士通株式会社 Method for forming marks for measuring dimensional behavior of prepreg

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816729U (en) * 1981-07-24 1983-02-02 シャープ株式会社 automatic paper feeder
JPS58169723U (en) * 1982-05-01 1983-11-12 アルパイン株式会社 radio receiver

Also Published As

Publication number Publication date
JPH0445294Y2 (en) 1992-10-26

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