JPH0445294Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a receiver having an automatic preset function and configured to control the local oscillation frequency using a PLL.

[Prior art and its problems]

Conventionally, such a receiver has been shown in FIG. 4.

In the figure, 1 is an antenna, 2 is a high frequency amplifier circuit (RF amplifier), 3 is a mixer, 4 is an intermediate frequency amplifier circuit (F amplifier), 5 is a detection circuit, 6 is an output amplifier, and 7 is a speaker.

Further, 8 is a PLL which uses pulses from an oscillator 10 to obtain a frequency division ratio in a binary counter 12 and performs tuning. Reference numeral 9 denotes a level detection circuit that determines whether or not the synchronization has been achieved. 14 is a memory for storing data of the frequency division ratio of PLL8, and 13 is a memory 14.
This is a counter for addressing.

Now, switch 1 to start automatic preset.
When 7 is pressed, the binary counter 12 and counter 13 are reset, then the RS flip-flop 11 is set, and the pulse passed through the AND gate 24 is applied to the binary counter 12,
The frequency division ratio of PLL8 changes.

The signal received by antenna 1 is sent to RF amplifier 2,
It passes through a mixer 3, an F amplifier 4, and a detection circuit 5. When tuned to the transmission frequency of the broadcasting station, the output of the level detection circuit 9 becomes High. Then, by the inverter 26 and the AND gate 25, the oscillator 1
At the falling edge of the 0 pulse, the output of the level detection circuit 9 is applied to the memory 14 as a memory write signal,
PLL frequency division ratio of binary counter 12 is memory 1
Written to 4.

The memory write signal passing through the delay circuit 23 is
The value of the counter 13 is incremented by one and the address of the memory 14 is updated.

The above operation continues until the overflow signal passes through the OR gate 28 and resets the RS flip-flop 11, either because the memory 14 is full and the counter 13 overflows, or because the binary counter 12 overflows after going around the receive band. Repeat the series of actions.

However, since conventional receivers are configured as described above, when the memory 14 becomes full, the automatic preset operation is canceled without going around the receiving band, and the remaining receiving bands are automatically preset. The drawback was that even if there was a broadcast station that could be received, it would be ignored.

[Purpose of invention]

The purpose of the present invention is to overcome the above-mentioned drawbacks of the conventional technology, and even if the memory for PLL frequency division ratio data becomes full during automatic presetting, the number of remaining broadcast stations that cannot be stored in the reception band can be reduced. The object of the present invention is to provide a receiver capable of displaying images.

〔Example〕

FIG. 1 is a block diagram of a receiver according to an embodiment of the present invention, FIG. 2 is a start/reset timing chart in parts a to d of FIG.
The figure is a timing chart of the count up in parts e to l of FIG. 1.

What is important in FIG. 1 is that, unlike the conventional receiver shown in FIG.
overflow output VF and EXR gate 29
The second
A counter 18 is provided, and data from the counter 18 is sent to a display 20 via a driver circuit 19.

That is, when a signal from a predetermined broadcasting station is received, the output e from the level detection circuit 9 becomes High. The clock pulse d from the oscillator 10 is connected to the signal from the level detection circuit 9 through the inverter 26.
Since AND25 is taken, the output f of AND gate 25 is High at the falling edge of clock pulse d.
becomes.

The write signal h to the memory 14 is sent to the counter 1
The signal j is obtained by inverting the overflow signal i of No. 3 by an inverter 27 and the signal f. At the same time, the signal f is transmitted to the delay circuit 23
The count up signal g of the counter 13 is
becomes. td in FIG. 3 is the delay time.

The above operation is repeated every time each broadcast station is received. Then, when the memory 14 becomes full and the overflow signal i is output from the counter 13,
With the signal j inverted by the inverter 27,
The output h of the AND gate 21 is lowered to Low to inhibit writing (WR) to the memory 14.

At the same time, the overflow signal i of the counter 13
and the output K of the EXR gate 29, and sends a counter up signal l to the counter 18.

The data of the counter 18 is output to the driver 19. Then, when the RS flip-flop 11 is reset by the overflow of the binary counter 12 after going around the receiving band, the output is
It becomes High and operates the driver 19.

As a result, the number of broadcast stations that have not been stored in the memory 14 will be displayed on the display 20.

At the same time as the above display, the first station that could not be memorized during automatic preset will be displayed as the last one.
If you scan the reception band from that station after presetting it as a memory, you can not only display the number of stations that were not stored in the memory, but also quickly change the memory to the desired station, which is more effective. .

[Effect of idea]

As explained above, according to the present invention, if there are more receivable broadcast stations in the reception band than the number of preset memories, the number of broadcast stations that were not stored in memory is displayed, so that the desired It is possible to easily change presets for broadcast stations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a receiver according to an embodiment of the present invention, FIG. 2 is a timing chart showing the start and reset of signals in parts a to d in FIG. 1, and FIG. 3 is a timing chart showing e in FIG. FIG. 4 is a timing chart showing the count up of signals in sections 1 to 1, and a block diagram of a conventional receiver. 8...PLL, 9...Level detection circuit, 10...
...Oscillator, 12...Binary counter, 13...
1st counter, 14...memory, 18...2nd
counter, 19...driver, 20...indicator.

Claims (1)

[Scope of Claim for Utility Model Registration] A phase lock loop that changes the local oscillation frequency according to its frequency division ratio, and data on the frequency division ratio of the phase lock loop for receivable broadcasting stations in different storage areas. and a memory having a counting capacity equal to the number of storage areas of this memory, and an address of a storage area of the memory that is to store data on the frequency division ratio of the phase lock loop for receivable broadcast stations. A receiver having an automatic preset function, which includes a first counter to be specified, a second counter that counts the number of overflow outputs of the first counter, and a display that displays the counted value of the second counter. and display the counted value of the second counter on the display when the sweep of the entire reception band is completed, thereby indicating the number of broadcast stations for which the frequency division ratio is not stored in the memory. A receiver characterized in that it displays.