JPH0458204B2 - - Google Patents

Info

Publication number
JPH0458204B2
JPH0458204B2 JP58048494A JP4849483A JPH0458204B2 JP H0458204 B2 JPH0458204 B2 JP H0458204B2 JP 58048494 A JP58048494 A JP 58048494A JP 4849483 A JP4849483 A JP 4849483A JP H0458204 B2 JPH0458204 B2 JP H0458204B2
Authority
JP
Japan
Prior art keywords
signal
level
frequency
level signal
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58048494A
Other languages
Japanese (ja)
Other versions
JPS59174014A (en
Inventor
Bunji Morya
Michio Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP4849483A priority Critical patent/JPS59174014A/en
Publication of JPS59174014A publication Critical patent/JPS59174014A/en
Publication of JPH0458204B2 publication Critical patent/JPH0458204B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
    • H03J1/0008Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【発明の詳細な説明】 技術分野 本発明はチユーナの受信局プリセツト装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a receiving station presetting device for a tuner.

背景技術 プリセツト選局自在なチユーナにあつては、予
めスキヤン又はシーク等の周波数掃引による受信
局探索機能を用いて受信信号を検知し、当該掃引
を一時中止してその時の受信周波数に対応した周
波数信号をメモリに記憶し、再び掃引を開始して
受信信号を検知して行くという方法がある。この
方法では、メモリの容量すなわち記憶領域数に限
界がある場合、受信バンドの全周波数に亘つて掃
引をなす前にメモリ容量を越えてしまうことがあ
り、よつて、掃引を行わなかつた残余の周波数帯
により大きな電界強度を有する放送局が存在して
いる時には、この放送局の受信がプリセツト選局
できないという欠点がある。
BACKGROUND TECHNOLOGY In the case of a tuner that can freely select preset channels, a received signal is detected in advance by using a reception station search function by frequency sweep such as scan or seek, and the sweep is temporarily stopped and the frequency corresponding to the reception frequency at that time is detected. One method is to store the signal in memory and start sweeping again to detect the received signal. In this method, if there is a limit to the memory capacity, that is, the number of storage areas, the memory capacity may be exceeded before sweeping over all the frequencies of the reception band, and therefore the remaining When there is a broadcasting station with a higher electric field strength in a frequency band, there is a drawback that preset selection cannot be performed for reception of this broadcasting station.

発明の概要 [発明の目的] 本発明はこのような従来のものの欠点を除去す
るためになされたもので、受信バンド内における
受信信号レベルが最大の放送局からメモリ容量の
範囲内で受信信号レベルの大小又は周波数の高低
順にてプリセツトすることができるチユーナの受
信局プリセツト装置を提供することを目的として
いる。
Summary of the Invention [Object of the Invention] The present invention has been made to eliminate the drawbacks of the conventional ones. It is an object of the present invention to provide a receiving station presetting device for a tuner that can preset in the order of magnitude or frequency.

[発明の概要] 本発明による受信局プリセツト装置は、予め記
憶されている受信局を示す信号をメモリから呼出
して選局をなすようにした自動選局可能なチユー
ナにおける受信局プリセツト装置であつて、受信
周波数バンド内の受信をなすべく受信周波数の掃
引をなす周波数掃引手段と、この掃引期間におい
て所定レベル以上の受信信号が得られたときにこ
の受信信号レベル及びその受信周波数を夫々表わ
すレベル信号及び周波数信号対を発生する信号発
生手段と、前記レベル信号及び周波数信号の対を
夫々前記レベル信号の大小の順に記憶する記憶手
段とを有し、 前記記憶手段が記憶すべき前記レベル信号の数
が前記記憶手段の容量を越えた時に、前記記憶手
段は記憶しているレベル信号群と前記信号発生手
段により現在発生せしめられている現レベル信号
とを比較してこの現レベルより小なる記憶レベル
信号群中の最大のレベル信号及びこれの後位にあ
るレベル信号を1順位ずつ後位にシフトした後当
該最大のレベル信号の直前の順位に前記現レベル
信号を配置することによつて前記現レベル信号及
びこれに対応する周波数信号対を含むレベル信号
群及び周波数信号対群を受信信号レベルの高低の
順に配列して記憶することを特徴としている。
[Summary of the Invention] A receiving station presetting device according to the present invention is a receiving station presetting device for a tuner capable of automatic channel selection, which selects a station by calling a pre-stored signal indicating a receiving station from a memory. , a frequency sweep means for sweeping the reception frequency to achieve reception within the reception frequency band; and a level signal representing the reception signal level and reception frequency, respectively, when a reception signal of a predetermined level or higher is obtained during this sweep period. and a signal generating means for generating a pair of frequency signals, and a storage means for storing the pairs of the level signal and the frequency signal in order of magnitude of the level signal, respectively, the number of the level signals to be stored by the storage means exceeds the capacity of the storage means, the storage means compares the stored level signal group with the current level signal currently generated by the signal generation means and selects a storage level smaller than this current level. By shifting the maximum level signal in the signal group and the level signals following it one rank at a time, and then placing the current level signal at the rank immediately before the maximum level signal, It is characterized in that a level signal group and a frequency signal pair group including a level signal and a frequency signal pair corresponding thereto are arranged and stored in the order of high and low received signal levels.

実施例 以下に本発明の実施例を図面に用いて説明す
る。
Embodiments Examples of the present invention will be described below with reference to the drawings.

第1図は本発明の実施例を示す概略ブロツク図
であり、アンテナ受信信号はフロントエンド1に
おいてIF(中間周波数)信号に変換されてIFアン
プ2に入力される。IFアンプ2の出力は検波器
3にて検波されオーデイオ信号に復調される。フ
ロントエンド1における図示せぬRF同調回路の
同調周波数や局部発振器の発振周波数がPLL(フ
エイズロツクドループ)回路4の出力により制御
されるようになつており、いわゆるPLLシンセ
サイザ方式のチユーナ構成とされている。
FIG. 1 is a schematic block diagram showing an embodiment of the present invention, in which an antenna reception signal is converted into an IF (intermediate frequency) signal at a front end 1 and input to an IF amplifier 2. As shown in FIG. The output of the IF amplifier 2 is detected by a detector 3 and demodulated into an audio signal. The tuning frequency of an RF tuning circuit (not shown) and the oscillation frequency of a local oscillator in the front end 1 are controlled by the output of a PLL (phase locked loop) circuit 4, and the tuner is configured using a so-called PLL synthesizer system. ing.

本例では、プリセツトメモリ動作指令のための
指令器5が設けられており、この指令出力により
掃引制御器6が活性化されて受信バンドの最小周
波数から最大周波数までの受信が可能なように、
PLL4への制御信号(PLL内のプログラマブル
デイバイダの分周比制御のための信号を指称す
る)が自動的に可変されて受信周波数の掃引が行
われるようになつている。
In this example, a command device 5 is provided to issue a preset memory operation command, and the command output activates a sweep controller 6 to enable reception from the minimum frequency to the maximum frequency of the reception band. ,
A control signal to the PLL 4 (designating a signal for controlling the division ratio of a programmable divider in the PLL) is automatically varied to sweep the reception frequency.

IFアンプ2におけるIFキヤリヤレベルがレベ
ル検出器7において検出されるが、予め設定され
た可聴限界点レベル以上のキヤリヤが存在してい
る時だけキヤリヤレベル検出信号が導出されるよ
うになつている。この検出信号はA/D(アナロ
グ−デイジタル信号)変換器8においてデイジタ
ル化されメモリR/W制御器9を介してLs信号
(IFキヤリヤレベルに対応したレベル信号)を記
憶するメモリ10へ書込まれる。この時の受信周
波数を示す周波数信号(fs信号とする)が掃引制
御器6から制御器9を介してfsメモリ11へ書込
まれる。
The IF carrier level in the IF amplifier 2 is detected by the level detector 7, and a carrier level detection signal is derived only when a carrier higher than a preset audible threshold level exists. This detection signal is digitized by an A/D (analog-digital signal) converter 8 and written to a memory 10 that stores an Ls signal (level signal corresponding to the IF carrier level) via a memory R/W controller 9. . A frequency signal (referred to as an fs signal) indicating the reception frequency at this time is written from the sweep controller 6 to the fs memory 11 via the controller 9.

メモリ回数計数機12が設けられており、メモ
リ10,11への書込回数が順次計数されてメモ
リ容量に書込回数が達した時に、所定信号を発生
して塩算処理器13へこの信号を送出する。この
演算処理器13においては、メモリ書込回数がメ
モリ容量を越えた場合、A/D変換器8からの現
Ls信号が以前に入力されて記憶されている現メ
モリ内容のLs信号と比較され、その最小値より
現Ls信号が更に小であれば何等メモリ内容を変
更せず、逆に最小値より大であれば最小値のLs
信号をメモリから除外してその代りにこの現Ls
信号をメモリへ書込む機能を有する。メモリ11
においても、その時の現fs信号が最小レベル信号
Lsに対応して記憶されているfs信号と置換される
のである。
A memory number counter 12 is provided, which sequentially counts the number of writes to the memories 10 and 11, and when the number of writes reaches the memory capacity, generates a predetermined signal and sends this signal to the salt calculation processor 13. Send out. In this arithmetic processor 13, when the number of memory writes exceeds the memory capacity, the current data from the A/D converter 8 is
The Ls signal is compared with the Ls signal of the current memory content that was previously input and stored, and if the current Ls signal is smaller than the minimum value, no change is made to the memory content; conversely, if it is larger than the minimum value, If so, the minimum value Ls
Remove the signal from memory and instead use this current Ls
It has the function of writing signals to memory. memory 11
, the current fs signal at that time is the minimum level signal.
It is replaced with the fs signal stored corresponding to Ls.

第2図は第1図のブロツク9〜13の動作を示
すフローチヤートである。指令器5からの指令信
号に応答して計数器12が「0」にリセツトされ
ると共に、受信バンドの最小周波数から掃引が開
始される(図のA,Bに相当)。Cのステツプに
おいて、最大周波数まで達したか否かが判断さ
れ、達していなければ受信状態となる。この受信
状態Dでは、局間ノイズを排除するためにオーデ
イオ出力がミユーテイングされるようになつてい
るが特に図示しない。
FIG. 2 is a flowchart showing the operations of blocks 9 to 13 in FIG. In response to a command signal from the command unit 5, the counter 12 is reset to "0" and the sweep is started from the minimum frequency of the receiving band (corresponding to A and B in the figure). In step C, it is determined whether the maximum frequency has been reached, and if it has not reached the maximum frequency, the receiving state is entered. In this receiving state D, the audio output is muted to eliminate inter-office noise, but this is not particularly shown.

Eにおいては、メモリへの書込回数がメモリ容
量(本例では5とする)に達したか否かが判別さ
れる。これは計数器12の出力により行われるよ
うになつている。メモリ容量5に達していない場
合はFへ進み、Ls及びfsの両信号が各メモリ1
0,11へ夫々書込まれる。この場合、Gに示す
ように各メモリ10,11においてはLs、fsのメ
モリ内容がIFキヤリヤレベルの大きい順に並べ
直される。この動作をLsレベルによるソート動
作と称し演算処理器13にて行われる。ステツプ
Hにおいて、計数器12の内容を1だけ増大せし
めて再びCのステツプへ進み以上の動作を繰返
す。
At E, it is determined whether the number of writes to the memory has reached the memory capacity (5 in this example). This is done by the output of the counter 12. If the memory capacity has not reached 5, proceed to F, and both Ls and fs signals are sent to each memory 1.
0 and 11, respectively. In this case, as shown in G, the memory contents of Ls and fs in each memory 10 and 11 are rearranged in descending order of IF carrier level. This operation is called a sorting operation based on the Ls level, and is performed by the arithmetic processor 13. At step H, the contents of the counter 12 are incremented by 1, and the process goes to step C again to repeat the above operations.

書込回数がメモリ容量を越えるとステツプIへ
移行し、その後のLs信号が現メモリ内容のLs信
号と比較され小であればステツプCへ戻る。一
方、現Ls信号が現メモリ内容のLs信号の少なく
とも1つよりも大であれば、Jへ移行して現Ls
信号はメモリ内容のLs信号のうちどれよりも大
であるかの判定が行われる。ここで、現Ls信号
LsNとし、メモリ内容のLs信号を大なるものか
ら順次Ls1,Ls2,Ls3,Ls4,Ls5とする
と、ステツプJにおいて、 Ls2>LsN>Ls3 と判定されれば、Ls3→Ls4、Ls4→Ls5、Ls
5→メモリから外す、という操作が行われる。そ
して、メモリ内の空いたLs3の箇所にLsNを書
込み新たなLs3と定義するが、fs用のメモリ11
においても同様なシフト及び置換がなされる。こ
れがK及びLのステツプであり、I〜Lが演算処
理器13にて行われるようになつている。しかる
後に再びステツプCへ戻る。
When the number of writes exceeds the memory capacity, the process moves to step I, and the subsequent Ls signal is compared with the Ls signal of the current memory contents, and if it is smaller, the process returns to step C. On the other hand, if the current Ls signal is larger than at least one of the Ls signals of the current memory contents, the current Ls signal is shifted to J.
It is determined whether the signal is larger than any of the Ls signals in the memory contents. Here, the current Ls signal
LsN, and the Ls signals in the memory contents are sequentially Ls1, Ls2, Ls3, Ls4, and Ls5 from largest to largest. If it is determined that Ls2>LsN>Ls3 in step J, then Ls3→Ls4, Ls4→Ls5, Ls
5→Remove from memory. Then, LsN is written to the empty Ls3 location in the memory and defined as a new Ls3, but the memory 11 for fs
Similar shifts and substitutions are made in . These are steps K and L, and I to L are performed by the arithmetic processor 13. After that, return to step C again.

受信周波数の掃引が最大周波数に達するとMへ
進み、受信レベル順にメモリ内で並べられていた
Ls及びfsデータを周波数順(周波数の低い順)に
並べるか(fsによるソート動作)否かを判断し
(外部指令による)、そうであればNでそのソート
動作をなす。そうでなければそのままプログラム
は終了することになるのである。
When the reception frequency sweep reaches the maximum frequency, it advances to M and is arranged in memory in order of reception level.
It is determined whether or not the Ls and fs data are arranged in frequency order (lowest frequency order) (sorting operation by fs) (based on an external command), and if so, N is used to perform the sorting operation. Otherwise, the program will simply terminate.

fsによるソートを行なえば、メモリ内容が周波
数の高低順に配列されることになり、プリセツト
番号の順が常に周波数の高低順となるようするこ
とが容易である。
By sorting by fs, the memory contents are arranged in order of high and low frequencies, and it is easy to ensure that the order of preset numbers is always in the order of high and low frequencies.

尚、第1図のブロツク9〜13はいわゆるマイ
クロコンピユータ等により容易に実現可能である
ことは明白である。
It is clear that blocks 9 to 13 in FIG. 1 can be easily realized by a so-called microcomputer or the like.

第3図はある地域における所定受信バンド内の
IFキヤリヤレベルの一例を示す図であり、この
例を用いて本発明のプリセツト装置の具体的動作
を説明する。最低周波数fminから掃引を開始す
ると、先ず可聴減退点VT以上の受信局aが受信
されそのLs及びfs信号を夫々Ls1,fs1としてメ
モリする。次に受信局bが受信され、同様にLs
2,fs2がメモリされるが、Ls1とLs2とのレ
ベル比較を行つてLs2がより大であるからb局
をLs1,fs1と定義しa局をLs2,fs2と定義し
て順次メモリする。c局はVTレベル以下である
ので無視されて、次の局d〜fを順次レベル順に
メモリすることになる。
Figure 3 shows the frequency within a given reception band in a certain area.
FIG. 3 is a diagram showing an example of an IF carrier level, and the specific operation of the preset device of the present invention will be explained using this example. When the sweep is started from the lowest frequency fmin, the receiving station a whose frequency is higher than the audible attenuation point VT is first received, and its Ls and fs signals are stored as Ls1 and fs1, respectively. Next, receiving station b is received, and similarly Ls
2 and fs2 are stored in memory, but a level comparison is made between Ls1 and Ls2, and since Ls2 is larger, station b is defined as Ls1 and fs1, station a is defined as Ls2 and fs2, and they are sequentially stored. Since station c is below the VT level, it is ignored, and the next stations d to f are stored in memory in order of level.

g局を受信とするとメモリ容量限界に達してい
るので、現メモリ内容の最小値の局aのデータを
メモリから除外し新たにgをメモリする。局hに
対しても同様である。以上の動作がLsソートで
あれば、メモリの各チヤンネルCH1〜CH5には、
順次d、g、h、e及びbとなる如く記憶され
る。fsソートであれば、各チヤンネルCH1〜CH5
には順次、b、d、e、g、hとなる如く記憶さ
れる。
When receiving station g, the memory capacity limit has been reached, so the data of station a, which has the minimum value of the current memory contents, is removed from the memory and a new station g is stored. The same applies to station h. If the above operation is Ls sort, each channel CH 1 to CH 5 of the memory has
They are stored sequentially as d, g, h, e, and b. For fs sorting, each channel CH 1 to CH 5
are stored sequentially as b, d, e, g, and h.

発明の効果 叙上と如く、本発明によれば受信局のプリセツ
トメモリが全て自由に行えると共に電界強度の高
い順にメモリ容量の範囲でプリセツト可能となる
から、いずれの受信エリアにあつても常に簡単に
電界強度の大きな放送局を受信するようにするこ
とができる。特に車載用チユーナでは受信エリア
が常に移動するので、本発明のプリセツト装置を
用いれば自動的に最適な受信局群のプリセツトメ
モリが可能となつてプリセツト操作の煩雑さがす
べて解消されることになる。また、レベルの高低
の順に従つて受信局情報をメモリするようにして
いる故受信者は高感度かつ受信レベル順での選局
を容易にし、更には選局表示動作をも容易にして
いる。
Effects of the Invention As described above, according to the present invention, all the preset memories of the receiving station can be freely performed and can be preset within the memory capacity in descending order of electric field strength. It is possible to easily receive broadcasting stations with large electric field strengths. In particular, since the reception area of an on-vehicle tuner constantly moves, using the preset device of the present invention will automatically store a preset memory of an optimal group of receiving stations, thereby eliminating all the complexity of preset operations. Become. In addition, since the received station information is stored in memory in the order of high and low levels, the receiver can easily select stations with high sensitivity and in the order of received levels, and furthermore, the operation of displaying the channel selection is also facilitated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すブロツク図、第
2図は本発明の実施例の動作を示すフローチヤー
ト、第3図は本発明の具体的動作を説明するため
の放送局の電界分布状態の例を示す図である。 主要部分の符号の説明、4……PLL、6……
掃引制御器、7……レベル検出器、10,11…
…メモリ、12……メモリ回数計数器、13……
演算処理器。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the embodiment of the present invention, and FIG. 3 is an electric field distribution of a broadcasting station to explain the specific operation of the present invention. It is a figure which shows the example of a state. Explanation of symbols of main parts, 4...PLL, 6...
Sweep controller, 7... Level detector, 10, 11...
...Memory, 12...Memory number counter, 13...
Arithmetic processor.

Claims (1)

【特許請求の範囲】 1 予め記憶されている受信局を示す信号をメモ
リから呼出して選局をになすようにした自動選局
可能なチユーナにおける受信局プリセツト装置で
あつて、受信周波数バンド内の受信をなすべく受
信周波数の掃引をなす周波数掃引手段と、この掃
引期間において所定レベル以上の受信信号が得ら
れたときにこの受信信号レベル及びその受信周波
数を夫々表わすレベル信号及び周波数信号対を発
生する信号発生手段と、前記レベル信号及び周波
数信号の対を夫々前記レベル信号の大小の順に記
憶する記憶手段とを有し、 前記記憶手段が記憶すべき前記レベル信号の数
が前記記憶手段の容量を越えた時に、前記記憶手
段は記憶しているレベル信号群と前記信号発生手
段により現在発生せしめられている現レベル信号
とを比較してこの現レベル信号より小なる記憶レ
ベル信号群中の最大のレベル信号及びこれの後位
にあるレベル信号を1順位ずつ後位にシフトした
後該最大のレベル信号の直前の順位に前記現レベ
ル信号を配置することによつて前記現レベル信号
及びこれに対応する周波数信号対を含むレベル信
号及び周波数信号対群を受信信号レベルの高低の
順に配列して記憶することを特徴とするプリセツ
ト装置。 2 前記記憶手段は、指令に従つて、既に記憶し
ているレベル信号及び周波数対群を周波数の高低
の順に配列し直すことを特徴とする特許請求の範
囲第1項記載のプリセツト装置。
[Scope of Claims] 1. A receiving station presetting device in a tuner capable of automatic tuning, in which a pre-stored signal indicative of a receiving station is recalled from a memory to select a station, which Frequency sweeping means sweeps the reception frequency to perform reception, and when a reception signal of a predetermined level or higher is obtained during this sweep period, generates a level signal and a frequency signal pair representing the reception signal level and its reception frequency, respectively. and storage means for storing pairs of the level signal and frequency signal in order of magnitude of the level signal, and the number of the level signals to be stored in the storage means is determined by the capacity of the storage means. , the storage means compares the stored level signal group with the current level signal currently generated by the signal generation means and determines the maximum level among the stored level signal groups that is smaller than the current level signal. The current level signal and the level signal following it are shifted backward by one rank, and then the current level signal is placed in the rank immediately before the highest level signal. A preset device characterized in that a level signal and a group of frequency signal pairs including corresponding frequency signal pairs are arranged and stored in the order of high and low received signal levels. 2. The preset device according to claim 1, wherein the storage means rearranges the already stored level signals and frequency pairs in order of high and low frequencies in accordance with a command.
JP4849483A 1983-03-23 1983-03-23 Memory system for tuner receiving station Granted JPS59174014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4849483A JPS59174014A (en) 1983-03-23 1983-03-23 Memory system for tuner receiving station

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4849483A JPS59174014A (en) 1983-03-23 1983-03-23 Memory system for tuner receiving station

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP11218594A Division JPH06318847A (en) 1994-04-27 1994-04-27 Reception station preset device for tuner

Publications (2)

Publication Number Publication Date
JPS59174014A JPS59174014A (en) 1984-10-02
JPH0458204B2 true JPH0458204B2 (en) 1992-09-16

Family

ID=12804932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4849483A Granted JPS59174014A (en) 1983-03-23 1983-03-23 Memory system for tuner receiving station

Country Status (1)

Country Link
JP (1) JPS59174014A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2574252B2 (en) * 1986-08-19 1997-01-22 パイオニア株式会社 Reception sensitivity control method of swept receiver
JPH063867B2 (en) * 1987-11-30 1994-01-12 アルパイン株式会社 Preset type car radio receiver
JPH0612867B2 (en) * 1987-12-04 1994-02-16 アルパイン株式会社 Car radio receiver
JP2966476B2 (en) * 1990-05-23 1999-10-25 パイオニア株式会社 Reception station preset method of radio receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57152833U (en) * 1981-03-20 1982-09-25

Also Published As

Publication number Publication date
JPS59174014A (en) 1984-10-02

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