JPH02143837U - - Google Patents
Info
- Publication number
- JPH02143837U JPH02143837U JP5276789U JP5276789U JPH02143837U JP H02143837 U JPH02143837 U JP H02143837U JP 5276789 U JP5276789 U JP 5276789U JP 5276789 U JP5276789 U JP 5276789U JP H02143837 U JPH02143837 U JP H02143837U
- Authority
- JP
- Japan
- Prior art keywords
- reception level
- memory
- frequency information
- local oscillation
- oscillation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000010355 oscillation Effects 0.000 claims description 3
- 230000004044 response Effects 0.000 claims 1
- 238000004904 shortening Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図は、本考案のシンセサイザー受信機のブ
ロツク図、第２図は、同じく表示器の正面図、第
３図は同じく制御回路の要部のプログラムを示す
フローチヤート、第４図は、同じく他の実施例に
対する説明図である。
８…局部発振回路、１０…受信レベル検出回路
、１３…プリセツト用メモリ、ＰＳ…プリセツト
スキヤンキー、１４…制御回路。
Fig. 1 is a block diagram of the synthesizer receiver of the present invention, Fig. 2 is a front view of the display, Fig. 3 is a flowchart showing the program of the main part of the control circuit, and Fig. 4 is the same. FIG. 7 is an explanatory diagram for another embodiment. 8... Local oscillation circuit, 10... Reception level detection circuit, 13... Preset memory, PS... Preset scan key, 14... Control circuit.
Claims (1)
の受信レベルを検出する受信レベル検出手段と、
複数の周波数情報を記憶するメモリと、該メモリ
から周波数情報の読み出しを行なうためのキー手
段と、該キー手段の操作により、前記メモリから
順次周波数情報を読み出して前記局部発振回路に
与え、夫々の情報について所定時間再生する制御
手段とを有するものにおいて、前記制御手段は、
前記受信レベル検出手段に基づく受信レベルの低
下に応答して前記再生時間を短くする時間可変手
段を有することを特徴とするシンセサイザー受信
機。 a local oscillation circuit configured with a PLL circuit; a reception level detection means for detecting the reception level of the receiving station;
a memory for storing a plurality of frequency information; a key means for reading frequency information from the memory; and operation of the key means to sequentially read frequency information from the memory and apply it to the local oscillation circuit; and a control means for reproducing information for a predetermined time, the control means comprising:
A synthesizer receiver comprising a time variable means for shortening the playback time in response to a decrease in the reception level based on the reception level detection means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5276789U JPH02143837U (en) | 1989-05-08 | 1989-05-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5276789U JPH02143837U (en) | 1989-05-08 | 1989-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02143837U true JPH02143837U (en) | 1990-12-06 |
Family
ID=31573356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5276789U Pending JPH02143837U (en) | 1989-05-08 | 1989-05-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02143837U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6361818B2 (en) * | 1980-07-15 | 1988-11-30 |
-
1989
- 1989-05-08 JP JP5276789U patent/JPH02143837U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6361818B2 (en) * | 1980-07-15 | 1988-11-30 |
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