JPS5868758U - fm radio receiver - Google Patents

fm radio receiver

Info

Publication number
JPS5868758U
JPS5868758U JP16259281U JP16259281U JPS5868758U JP S5868758 U JPS5868758 U JP S5868758U JP 16259281 U JP16259281 U JP 16259281U JP 16259281 U JP16259281 U JP 16259281U JP S5868758 U JPS5868758 U JP S5868758U
Authority
JP
Japan
Prior art keywords
radio receiver
circuit
signal
detects
synchronous detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16259281U
Other languages
Japanese (ja)
Inventor
泰雄 川上
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP16259281U priority Critical patent/JPS5868758U/en
Publication of JPS5868758U publication Critical patent/JPS5868758U/en
Pending legal-status Critical Current

Links

Landscapes

  • Circuits Of Receivers In General (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案によるＦＭラジオ受信機の一実施例を示す
ブロック図である。 １１・・・ステレオ復調回路、１２・・・デコーダ回路
、−１２３・・・同期検波回路、１３・・・インターフ
ェース回路、ＶＣＯ・・・電圧制御発振器。The drawing is a block diagram showing an embodiment of an FM radio receiver according to the present invention. DESCRIPTION OF SYMBOLS 11... Stereo demodulation circuit, 12... Decoder circuit, -123... Synchronous detection circuit, 13... Interface circuit, VCO... Voltage controlled oscillator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フェーズロックループ方式のステレオ復調回路と、ＦＭ
放送信号の搬送波をＦＭ変調して放送局から送出される
情報信号を検出するデコーダ回路とを備えるＦＭラジオ
受信機において、前記デコ−ダ回路が前記情報信号の検
波を行う同期検波回路を有し、この同期検波回路の基準
周波数信号を前記ステレオ復調回路中の電圧制御発振器
の発振信号から作成することを特徴とするＦＭラジオ受
信機。Phase-locked loop stereo demodulation circuit and FM
An FM radio receiver comprising a decoder circuit that FM modulates a carrier wave of a broadcast signal and detects an information signal sent from a broadcast station, wherein the decoder circuit has a synchronous detection circuit that detects the information signal. , an FM radio receiver characterized in that a reference frequency signal of the synchronous detection circuit is created from an oscillation signal of a voltage controlled oscillator in the stereo demodulation circuit.
JP16259281U 1981-11-02 1981-11-02 fm radio receiver Pending JPS5868758U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16259281U JPS5868758U (en) 1981-11-02 1981-11-02 fm radio receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16259281U JPS5868758U (en) 1981-11-02 1981-11-02 fm radio receiver

Publications (1)

Publication Number Publication Date
JPS5868758U true JPS5868758U (en) 1983-05-10

Family

ID=29954901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16259281U Pending JPS5868758U (en) 1981-11-02 1981-11-02 fm radio receiver

Country Status (1)

Country Link
JP (1) JPS5868758U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5185396A (en) * 1975-01-23 1976-07-26 Nippon Denso Co
JPS52107710A (en) * 1976-03-05 1977-09-09 Matsunaga Tsuushiyou Kk Traffic decoder
JPS533484B2 (en) * 1971-10-18 1978-02-07

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS533484B2 (en) * 1971-10-18 1978-02-07
JPS5185396A (en) * 1975-01-23 1976-07-26 Nippon Denso Co
JPS52107710A (en) * 1976-03-05 1977-09-09 Matsunaga Tsuushiyou Kk Traffic decoder

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