JPS59171437U - squelch circuit - Google Patents
squelch circuitInfo
- Publication number
- JPS59171437U JPS59171437U JP6582783U JP6582783U JPS59171437U JP S59171437 U JPS59171437 U JP S59171437U JP 6582783 U JP6582783 U JP 6582783U JP 6582783 U JP6582783 U JP 6582783U JP S59171437 U JPS59171437 U JP S59171437U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- switching
- time constant
- time
- squelch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のスケルチ回路のブロック図、第２図は本
考案になるスケルチ回路の一実施例にお・ける一部に具
体的な回路を含んで示したブロック図である。
図中符号１はスケルチ回路、２は雑音整流回路、３は時
定数回路、４はスイッチング回路、５はアンテナ、６は
高周波増幅器、７は混合器、８は局部発振器、９は受信
周波数切換器（切換器）、 ・１０は中間周波増幅
器、１１は検波器、１２は開閉器、１３は雑音検出フィ
ルタ、１４はスケルチ回路、１５は切換時点検出回路、
１６は増幅器、１７は微分回路、１８は波形整形回路、
１９は時定数短縮回路、２０は検出用切換器である。FIG. 1 is a block diagram of a conventional squelch circuit, and FIG. 2 is a block diagram showing an embodiment of the squelch circuit according to the present invention, including some specific circuits. In the figure, 1 is a squelch circuit, 2 is a noise rectifier circuit, 3 is a time constant circuit, 4 is a switching circuit, 5 is an antenna, 6 is a high frequency amplifier, 7 is a mixer, 8 is a local oscillator, and 9 is a reception frequency switcher (switcher), 10 is an intermediate frequency amplifier, 11 is a detector, 12 is a switch, 13 is a noise detection filter, 14 is a squelch circuit, 15 is a switching point detection circuit,
16 is an amplifier, 17 is a differentiation circuit, 18 is a waveform shaping circuit,
19 is a time constant shortening circuit, and 20 is a detection switch.
Claims (1)
スケルチ回路とを設けた受信回路において、前記受信周
波数切換手段による切換開始を検出する切換時点検出手
段と、前記切換時点検出手段で得た検出情報にもとづき
、上記時定数回路の時定数を短縮する時定数短縮手段と
を具備し、受信周波数切換時点の誤動作を防止するよう
構成したことを特徴とするスケルチ回路。In a receiving circuit provided with receiving frequency switching means and a squelch circuit having a time constant circuit for preventing malfunction, switching time detection means detects the start of switching by the receiving frequency switching means, and detection information obtained by the switching time detection means. 1. A squelch circuit comprising time constant shortening means for shortening the time constant of the time constant circuit, and configured to prevent malfunctions at the time of switching the reception frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6582783U JPS59171437U (en) | 1983-04-30 | 1983-04-30 | squelch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6582783U JPS59171437U (en) | 1983-04-30 | 1983-04-30 | squelch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59171437U true JPS59171437U (en) | 1984-11-16 |
| JPS6324671Y2 JPS6324671Y2 (en) | 1988-07-06 |
Family
ID=30196037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6582783U Granted JPS59171437U (en) | 1983-04-30 | 1983-04-30 | squelch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59171437U (en) |
-
1983
- 1983-04-30 JP JP6582783U patent/JPS59171437U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6324671Y2 (en) | 1988-07-06 |
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