JPS6194359U - - Google Patents
Info
- Publication number
- JPS6194359U JPS6194359U JP1984180386U JP18038684U JPS6194359U JP S6194359 U JPS6194359 U JP S6194359U JP 1984180386 U JP1984180386 U JP 1984180386U JP 18038684 U JP18038684 U JP 18038684U JP S6194359 U JPS6194359 U JP S6194359U
- Authority
- JP
- Japan
- Prior art keywords
- soldered
- array type
- opposite side
- mounting surface
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
第1図はICチツプを実装したこの考案のプラ
スチツク製ピングリツドアレイ型パツケージの一
実施例を示す断面図、第2図は他の実施例を示す
断面図、第3図a,bは金属環の形状を示す平面
図である。 11,11a,11″…ガラス布基材高耐熱性
樹脂銅張積層板、11′…封止用樹脂流出防止用
枠板、12…ボンデイング端子、13…回路、1
4…金属環、15…スルホール穴、16…ランド
、17…リードピン、18…金属板、19…ダイ
パツト、20…クリーム半田、21…金属パツド
、22…ICチツプ、23…ポツテイング樹脂、
26…金属ワイヤ。
スチツク製ピングリツドアレイ型パツケージの一
実施例を示す断面図、第2図は他の実施例を示す
断面図、第3図a,bは金属環の形状を示す平面
図である。 11,11a,11″…ガラス布基材高耐熱性
樹脂銅張積層板、11′…封止用樹脂流出防止用
枠板、12…ボンデイング端子、13…回路、1
4…金属環、15…スルホール穴、16…ランド
、17…リードピン、18…金属板、19…ダイ
パツト、20…クリーム半田、21…金属パツド
、22…ICチツプ、23…ポツテイング樹脂、
26…金属ワイヤ。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 半導体用プラスチツク製ピングリツドアレ
イ型パツケージにおけるICチツプ搭載面の反対
側に金属板を半田接合したことを特徴とするプラ
スチツク製ピングリツドアレイ型パツケージ。 (2) 金属板はICチツプ搭載面の反対側に形成
した金属製パツド部に半田接合したことを特徴と
する実用新案登録請求の範囲第1項記載のプラス
チツク製ピングリツドアレイ型パツケージ。 (3) 金属板はICチツプ搭載面の反対側周囲に
形成した金属環に半田接合したことを特徴とする
実用新案登録請求の範囲第1項記載のプラスチツ
ク製ピングリツドアレイ型パツケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984180386U JPS6194359U (ja) | 1984-11-27 | 1984-11-27 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984180386U JPS6194359U (ja) | 1984-11-27 | 1984-11-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6194359U true JPS6194359U (ja) | 1986-06-18 |
Family
ID=30737942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984180386U Pending JPS6194359U (ja) | 1984-11-27 | 1984-11-27 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6194359U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62196855A (ja) * | 1986-02-22 | 1987-08-31 | Ibiden Co Ltd | 半導体搭載用基板 |
JPH02278856A (ja) * | 1989-04-20 | 1990-11-15 | Nec Corp | 半導体集積回路装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58159355A (ja) * | 1982-03-17 | 1983-09-21 | Nec Corp | 半導体装置の製造方法 |
-
1984
- 1984-11-27 JP JP1984180386U patent/JPS6194359U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58159355A (ja) * | 1982-03-17 | 1983-09-21 | Nec Corp | 半導体装置の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62196855A (ja) * | 1986-02-22 | 1987-08-31 | Ibiden Co Ltd | 半導体搭載用基板 |
JPH02278856A (ja) * | 1989-04-20 | 1990-11-15 | Nec Corp | 半導体集積回路装置 |
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