JPS618976A - Method for forming gate electrode of field effect transistor - Google Patents
Method for forming gate electrode of field effect transistorInfo
- Publication number
- JPS618976A JPS618976A JP12977084A JP12977084A JPS618976A JP S618976 A JPS618976 A JP S618976A JP 12977084 A JP12977084 A JP 12977084A JP 12977084 A JP12977084 A JP 12977084A JP S618976 A JPS618976 A JP S618976A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric film
- gate electrode
- forming
- film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 9
- 230000005669 field effect Effects 0.000 title claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010931 gold Substances 0.000 claims abstract description 13
- 229910052737 gold Inorganic materials 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims abstract description 13
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 235000008331 Pinus X rigitaeda Nutrition 0.000 claims description 7
- 235000011613 Pinus brutia Nutrition 0.000 claims description 7
- 241000018646 Pinus brutia Species 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 239000010936 titanium Substances 0.000 abstract description 3
- 229910052719 titanium Inorganic materials 0.000 abstract description 3
- 235000001674 Agaricus brunnescens Nutrition 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000001020 plasma etching Methods 0.000 abstract 1
- 239000010953 base metal Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は電界効果トランジスタのゲート電極形成方法
に係り、特にマツシュルーム形微細ゲート電極の形成方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming a gate electrode of a field effect transistor, and particularly to a method for forming a fine mushroom-shaped gate electrode.
以下、ヒ化ガリウム（ＧａＡｓ ） Ｉ！、界効果トラ
ンジスタ（ＦＥＴ）を例にとって説明する。第１図Ａ、
Ｂはマツシュルーム形微細ゲート電極の従来の形成方法
の一例の主要段階における状態を示す断面図で、表面動
作層（特に図示せず）を有するＧａＡｓウェーハ（１）
上に第１のホトレジスト膜（２）を塗布形成し、写真製
版技術によってゲート電極パターンに対応する微細開孔
を形成し、その開孔内を含めて全上面にチタン・金など
からなるメッキ下地金属膜（３）を蒸着によって形成し
、続いて、ゲート電極形成領域を残して第２のホトレジ
ス）膜（４）で上面を被覆し、その後に下地金属膜（３
）を電極として電解金メッキでマツシュルーム形ゲート
電極（５）を形成する（第１図Ａ）Ｏつづいて、第１お
よび第２のホトレジスト膜（２１、（４）並びにこれら
に挾まれた部分のメッキ下地金属膜（３）を除去してマ
ツシュルーム形ゲート電極（５）を完成していた（第１
図Ｂ）。Below, gallium arsenide (GaAs) I! , a field effect transistor (FET) will be explained as an example. Figure 1A,
B is a cross-sectional view illustrating the main stages of an example of a conventional method for forming a fine pine mushroom-shaped gate electrode, in which a GaAs wafer (1) with a surface active layer (not particularly shown)
A first photoresist film (2) is applied and formed on the top, and fine holes corresponding to the gate electrode pattern are formed using photolithography, and a plating base made of titanium, gold, etc. is applied to the entire top surface, including the inside of the hole. A metal film (3) is formed by vapor deposition, and then the upper surface is covered with a second photoresist film (4) leaving the gate electrode formation region, and then a base metal film (3) is formed.
) is used as an electrode to form a pine mushroom-shaped gate electrode (5) by electrolytic gold plating (Fig. 1A). Next, the first and second photoresist films (21, (4) and the portions sandwiched between them are plated). The underlying metal film (3) was removed to complete the pine mushroom-shaped gate electrode (5) (first
Figure B).
このようにして得られるマツシュルーム形ゲート電極（
５）はその断面積が通常のゲート電極の場合に比して飛
躍的に大きくなるので、ゲート金属による抵抗Ｒｇを低
減することが可能となシ、素子の高周波性能を向上させ
ることができる０ところが、このようにマツシュルーム
形ゲート電極は電解金メッキによって形成されるので、
上記従来の方法では、その電解金メッキ層成長−に横方
向に大きな応力が作用し、第１のホトレジストの所望の
サブミクロン長に押えることが困難となるという欠点が
あった０
「
また、パターンの横方内拡がりを防止するために１第１
のホトレジスト膜（２）の代りに、窒化シリコン（８１
３Ｎ４）膜または酸化シリコン（Ｓ１０□）膜のよ−う
な誘電体膜を用いることもできるが、この場合はゲート
電極パターンの開孔を形成する際のドライエツチングに
おけるサイドエツチング効果によってホトレジストを用
いる場合のようには０．５μｍ以下の微細加工が困難で
ある０
〔発明の概要〕
この発明は以上のような点に鑑みてなされたもので、上
述の誘電体膜を用い、これに開孔を形成した後に、その
開孔の内側壁に他の誘電体からなるサイドウオールを被
着させることによってサブミクロンの孔を得て、この内
側へ電解金メッキで電極を成長させるので、実効ゲート
長が０．５μｍ以下のマツシュルーム形ゲート電極の形
゛成方法を提供するものである。Pine mushroom-shaped gate electrode obtained in this way (
5) Since its cross-sectional area is dramatically larger than that of a normal gate electrode, it is possible to reduce the resistance Rg due to the gate metal and improve the high frequency performance of the device. However, since the pine mushroom-shaped gate electrode is formed by electrolytic gold plating,
The conventional method described above has the disadvantage that a large stress acts in the lateral direction on the growth of the electrolytic gold plating layer, making it difficult to suppress the length of the first photoresist to the desired submicron length. 1. To prevent horizontal inward expansion.
Instead of the photoresist film (2), silicon nitride (81
It is also possible to use a dielectric film such as a 3N4) film or a silicon oxide (S10□) film, but in this case, when using a photoresist due to the side etching effect during dry etching when forming the opening of the gate electrode pattern. [Summary of the Invention] This invention has been made in view of the above points, and uses the above-mentioned dielectric film and forms holes in it. After the formation, a submicron hole is obtained by depositing a sidewall made of another dielectric material on the inner wall of the opening, and an electrode is grown inside this by electrolytic gold plating, so that the effective gate length is 0. The present invention provides a method for forming a mushroom-shaped gate electrode having a diameter of .5 μm or less.
第２図Ａ−Ｄはこの発明の一実施例の主要段階における
状態を示す断面図で、表面部に動作層を有するＧａＡｓ
ウェー−（１）上を第１の誘電体膜（６）で被 □“
１覆し、写真製版技術によってゲート電極形成部位に開
孔（７）をドライエツチングで形成し、続いて、開孔（
７）の内面を含めて全上面に第２の誘電体膜（８）を被
着させる（第２図Ａ）０次に１第２の誘電体膜（８）に
リアクチ仁かイオン・エツチング法によるエツチングを
施して、上記開孔（７）の側壁部に第２の誘電体からな
るサイドウオール（８ａ）を残す（第２図Ｂ）ｏ以下は
従来と同様に、サイドウオール（８ａ）の内面、その底
面に露出する（）ａＡｓウェーハ（１）の上面および第
１の誘電体膜（６）の上面にわたってチタン・金などか
らなるメッキ下地金属膜（３）を蒸着形成し、つづいて
、ゲート電極形成領域を残してホトレジスト膜（４）
”’ｑ上面を被覆し、その後に、下地金属膜（３）を電
極として電解金メッキを施してマツシュルーム形ゲート
電極（５）を形成する（第２図Ｃ）。つづいて、第１の
誘電体膜（６）、サイドウオール部（８ａ）、ホトレジ
２）膜（４）およびその下の部分のメッキ下地金属膜（
３）を除去して、マツシュルーム形ゲート電極（５）は
完成する（第２図Ｄ）。FIGS. 2A-2D are cross-sectional views showing the main stages of an embodiment of the present invention.
Cover the wave (1) with the first dielectric film (6) □“
1, an opening (7) is formed by dry etching at the gate electrode formation site using photolithography technology, and then an opening (7) is formed at the gate electrode formation site by dry etching.
7) Deposit the second dielectric film (8) on the entire upper surface including the inner surface (Fig. 2A) Next, apply the reactive or ion etching method to the second dielectric film (8). etching to leave a sidewall (8a) made of the second dielectric material on the side wall of the opening (7) (Fig. 2B). A plating base metal film (3) made of titanium, gold, etc. is formed by vapor deposition over the upper surface of the aAs wafer (1) and the upper surface of the first dielectric film (6) exposed on the inner surface and the bottom surface thereof, and then, Photoresist film (4) leaving the gate electrode formation area
``'q upper surface is coated, and then electrolytic gold plating is applied using the base metal film (3) as an electrode to form a mushroom-shaped gate electrode (5) (Fig. 2C).Subsequently, the first dielectric material Film (6), sidewall part (8a), photoresist 2) film (4) and the underlying metal film for plating (
3), the mushroom-shaped gate electrode (5) is completed (FIG. 2D).
この実施例において、第２、の誘電体膜（８）の成膜お
よび加工をすべてドライ工程で処理できるので、その厚
さとドライエツチング条件を微細にコントロールするこ
とによって、サイドウオール（８ａ）の厚さも再現性よ
く制御することができ、その結果第２図りに示す実効ゲ
ート長１ｇｌを所望の０．５μｍ以下のザブεクロンゲ
ート長に設定することが可能となり、しかも、マツシュ
ルーム形形状をしているので、サブミクロン化によるゲ
ート抵抗Ｒｇの増大をきたすこともない。In this example, since the formation and processing of the second dielectric film (8) can all be performed in a dry process, by finely controlling its thickness and dry etching conditions, the thickness of the sidewall (8a) can be Moreover, it can be controlled with good reproducibility, and as a result, it is possible to set the effective gate length 1gl shown in the second diagram to the desired sub-epsilon gate length of 0.5 μm or less. Therefore, the gate resistance Rg does not increase due to submicronization.
〔発明の効果〕−゛
以上説明したように、との発明では第１の誘電体膜のゲ
ート電極形成部位に開孔を形成し、その開孔の内側壁に
第２の誘電体からなるサイドウオールを選択的に被着さ
せ、−その内側へ電解金メッキでゲート金属層を成長さ
せるので、実効ゲート長が０．５μｍ以下のマツシュル
ーム形ゲート電極を再現性よく得ることができる。[Effects of the Invention] - As explained above, in the invention, an opening is formed in the gate electrode formation region of the first dielectric film, and a side surface made of the second dielectric is formed on the inner wall of the opening. Since the wall is selectively deposited and the gate metal layer is grown on the inside thereof by electrolytic gold plating, a mushroom-shaped gate electrode with an effective gate length of 0.5 μm or less can be obtained with good reproducibility.
第１図Ａ、Ｂはマツ“シュルーム形ゲート電極の□従来
の形成方法の一例の主要段階における状態を示す断面図
、第２図Ａ−Ｄはこの発明の一実施例の主要段階におけ
る状態を示す断面図である。
図において、（１）は半導体（ＧａＡｓ ）ウェーハ、
（３）はメ２ツキ下地金属膜、（５）はマツシュルーム
形ゲート電極、（６）は第１の誘電体膜、（７）は開孔
、（８）は第２の誘電体膜、（８，ａ）はサイドウオー
ルである。
なお、図中同一符号は同一または和尚部分を示す０Figures 1A and 1B are cross-sectional views showing the main stages of an example of a conventional method for forming a pine shroom-shaped gate electrode, and Figures 2A-D show the main stages of an embodiment of the present invention. In the figure, (1) is a semiconductor (GaAs) wafer;
(3) is a mesh base metal film, (5) is a mushroom-shaped gate electrode, (6) is a first dielectric film, (7) is an opening, (8) is a second dielectric film, ( 8, a) is the side wall. In addition, the same reference numerals in the figures indicate the same or Buddhist priest parts.
Claims (3)
の誘電体膜を形成する工程、この第１の誘電体膜のゲー
ト電極形成部位に開孔を形成する工程、この開孔内を含
めて上記第１の誘電体膜上に第２の誘電体膜を形成した
後にこの第２の誘電体膜に上方から異方性ドライエッチ
ングを施して上記開孔の内側壁にのみ上記第２の誘電体
からなるサイドウォールを残す工程、及びこのサイドウ
ォールによつて狭められた上記開孔内に電解金メッキに
よつて金を堆積させマツシユルーム形ゲート電極を形成
する工程を備えた電界効果トランジスタのゲート電極形
成方法。(1) A first layer is placed on a semiconductor wafer having an active layer on the surface.
a step of forming a dielectric film on the first dielectric film, a step of forming an opening in the gate electrode formation region of the first dielectric film, and a step of forming a second dielectric film on the first dielectric film including the inside of the opening. After forming the film, the second dielectric film is subjected to anisotropic dry etching from above to leave a sidewall made of the second dielectric only on the inner wall of the opening, and A method for forming a gate electrode of a field effect transistor, comprising the step of depositing gold by electrolytic gold plating in the narrowed opening to form a pine room-shaped gate electrode.
ことを特徴とする特許請求の範囲第１項記載の電界効果
トランジスタのゲート電極形成方法。(2) A method for forming a gate electrode of a field effect transistor according to claim 1, characterized in that silicon nitride is used for the first and second dielectrics.
ことを特徴とする特許請求の範囲第１項記載の電界効果
トランジスタのゲート電極形成方法。(3) A method for forming a gate electrode of a field effect transistor according to claim 1, characterized in that silicon oxide is used for the first and second dielectrics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12977084A JPS618976A (en) | 1984-06-23 | 1984-06-23 | Method for forming gate electrode of field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12977084A JPS618976A (en) | 1984-06-23 | 1984-06-23 | Method for forming gate electrode of field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS618976A true JPS618976A (en) | 1986-01-16 |
Family
ID=15017776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12977084A Pending JPS618976A (en) | 1984-06-23 | 1984-06-23 | Method for forming gate electrode of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS618976A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63171A (en) * | 1986-06-19 | 1988-01-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07183312A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Forming method of gate electrode for field-effect transistor |
| KR100429515B1 (en) * | 2001-12-27 | 2004-05-03 | 삼성전자주식회사 | Fabrication method for optical communication elements with mushroom type plating layer |
| JP2008053053A (en) * | 2006-08-24 | 2008-03-06 | Yokogawa Electric Corp | Wrong insertion prevention structure |
| JP2010535415A (en) * | 2007-07-31 | 2010-11-18 | リニューアブル・エナジー・コーポレーション・エーエスエー | Method for providing a contact on the back surface of a solar cell, and solar cell having a contact provided by the method |
-
1984
- 1984-06-23 JP JP12977084A patent/JPS618976A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63171A (en) * | 1986-06-19 | 1988-01-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07183312A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Forming method of gate electrode for field-effect transistor |
| KR100429515B1 (en) * | 2001-12-27 | 2004-05-03 | 삼성전자주식회사 | Fabrication method for optical communication elements with mushroom type plating layer |
| JP2008053053A (en) * | 2006-08-24 | 2008-03-06 | Yokogawa Electric Corp | Wrong insertion prevention structure |
| JP2010535415A (en) * | 2007-07-31 | 2010-11-18 | リニューアブル・エナジー・コーポレーション・エーエスエー | Method for providing a contact on the back surface of a solar cell, and solar cell having a contact provided by the method |
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